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Design and Physical Layout for a Multiplexor Array

IP.com Disclosure Number: IPCOM000113669D
Original Publication Date: 1994-Sep-01
Included in the Prior Art Database: 2005-Mar-27
Document File: 4 page(s) / 103K

Publishing Venue

IBM

Related People

Boury, B: AUTHOR [+3]

Abstract

Described is a very dense multiplexor circuit for use in Complimentary Metal Oxide Semiconductor (CMOS) circuits. The physical layout of the multiplexor accommodates maximum circuit density in a given area. A number of parallel input data lines extend in a direction perpendicular to the direction in which a number of parallel output data lines extend, with the array being formed by repeating a single clocked inverter cell in both these directions. This type of design facilitates the configuration of an array according to a desired number of input busses and a desired data width.

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Design and Physical Layout for a Multiplexor Array

      Described is a very dense multiplexor circuit for use in
Complimentary Metal Oxide Semiconductor (CMOS) circuits.  The
physical layout of the multiplexor accommodates maximum circuit
density in a given area.  A number of parallel input data lines
extend in a direction perpendicular to the direction in which a
number of parallel output data lines extend, with the array being
formed by repeating a single clocked inverter cell in both these
directions.  This type of design facilitates the configuration of an
array according to a desired number of input busses and a desired
data width.

   Fig. 1 is a schematic view of a clocked inverter circuit used in
the multiplexor array.

   Fig. 2 is a simplified schematic view of the circuit of Fig. 1.

   Fig. 3 is a schematic view of an array for a 4-bit, 4-to-1
multiplexor, formed by arraying the circuit of Figs. 1 and 2 into a 4
x 4 matrix.  The outputs of the clocked inverter cells in each column
are connected together to form a tri-state output bus.  The decoder
selects only a single row by means of the selection signals, -SELn
and +SELn, guaranteeing that one and only one clocked inverter output
is enabled on the tri-state output bus at a time.  This bus is
connected to the input of an inverter, which restores the proper
polarity of the input data.

      Fig. 4 is a plan view of the physical design of the multiplexor
array of Fig. 3.  Adjacent transistors ...