Browse Prior Art Database

Loop Breaking and Clock Gating Tests in Timing Analysis

IP.com Disclosure Number: IPCOM000113670D
Original Publication Date: 1994-Sep-01
Included in the Prior Art Database: 2005-Mar-27
Document File: 2 page(s) / 59K

Publishing Venue

IBM

Related People

Hathaway, DJ: AUTHOR

Abstract

A method is described for performing a conservative timing analysis on a cyclic logic network in linear time. The method also automatically determines tests which should be performed on clock gating signals. No information is required from any special delay rules.

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Loop Breaking and Clock Gating Tests in Timing Analysis

      A method is described for performing a conservative timing
analysis on a cyclic logic network in linear time.  The method also
automatically determines tests which should be performed on clock
gating signals.  No information is required from any special delay
rules.

      The novelty in this method derives from special treatment of
certain edges in a delay graph (loop breaking edges in the case of
cyclic timing analysis and edges from gate inputs to clock gate
outputs in the case of clock gate analysis).  In each case, arrival
time at the sink of the edge is computed without considering the
effect of the edge.  The contribution of the delay edge to the
required time at the source of the edge is the arrival time at the
edge sink minus the edge delay, rather than the required time at the
edge sink minus the edge delay.

Basic steps for using this method in timing analysis of cyclic
networks are as follows:
  1.  Generate a delay graph using the normal (functional) delay
models
      of the circuits and identify cycles in the logic network.
      Well-known techniques can be used, e.g., recursive depth-first
      search or forward levelization.
  2.  Identify a set of edges in the delay graph which break all
cycles
      in the network.  Because logic designers who will use the
timing
      analysis are familiar with paths broken at latches, loop
breaking
      edges at flush paths through latches (paths from data input to
      data output) are preferred.
  3.  Compute arrival times in the network without considering the
loop
      breaking e...