Browse Prior Art Database

Pre-Composed Superscalar Architecture

IP.com Disclosure Number: IPCOM000113673D
Original Publication Date: 1994-Sep-01
Included in the Prior Art Database: 2005-Mar-27
Document File: 6 page(s) / 237K

Publishing Venue

IBM

Related People

Jones Jr, GD: AUTHOR [+2]

Abstract

All modern Digital Signal Processors (DSPs) use compound instructions to achieve high performance. Compound instructions are distinguished by the fact that they cause multiple execute actions (two or more) to take place. They, thus, significantly increase performance in terms of execute operations-per-cycle when they are used. Performing a data transfer, multiplication, and ALU operation per cycle results in the current. Three operations per instruction cycle is typical of, and is a requirement for, competitive DSPs today. As performance demands continue to increase because of the requirement to execute more demanding and complex algorithms, future architectures will require a larger number of execute operations per instruction cycle and further specialization to be competitive.

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Pre-Composed Superscalar Architecture

      All modern Digital Signal Processors (DSPs) use compound
instructions to achieve high performance.  Compound instructions are
distinguished by the fact that they cause multiple execute actions
(two or more) to take place.  They, thus, significantly increase
performance in terms of execute operations-per-cycle when they are
used.  Performing a data transfer, multiplication, and ALU operation
per cycle results in the current.  Three operations per instruction
cycle is typical of, and is a requirement for, competitive DSPs
today.  As performance demands continue to increase because of the
requirement to execute more demanding and complex algorithms, future
architectures will require a larger number of execute operations per
instruction cycle and further specialization to be competitive.

However, the trend to increasing performance by adding more
arithmetic operations per cycle is severely impacted by the current
approach of using compound or multiple-execution instructions.  The
problem with these instructions as a class is that they become more
complicated as the number of operations they are intended to control
is increased.

      Here an architecture for signal processing is defined based on
the concept of instruction composition.  The basis for this
architecture is the inclusion of a portion of instruction address
space on-chip with the signal processor.  In this arrangement, the
on-chip instruction memory is configured so that each address, or
line, contains an integral number of conventional instructions.
Instructions can be composed, line by line, in this memory by loading
and concatenating simplex or single-action instructions from external
instruction memory.  Each internal instruction line is then
considered to be a single long instruction with multiple execute
actions that can all occur simultaneously in one cycle.  By following
this technique, the requirement that the base instruction set contain
increasingly complex compound, or multiple-action, instructions is
avoided as is the programming complexity that they foster.

      The Figure shows a proposed data flow which includes a segment
of on-chip instruction memory.  Since instruction memory locations
on-chip can be of any practical width, the limits on instruction word
size are effectively eliminated for those instructions stored
on-chip.  This creates the possibility of including very-complex
compound instructions in programs or subroutines that will be
executed out of on-chip storage.  These on-chip instructions can be
formed by concatenating multiple simplex instructions into one
instruction with multiple execute operations in a single cycle, in a
straight-forward and expandable way.  Such instructions would have
the capacity to control all the elements of a processor data flow to
their fullest extent, and that control can be orthogonal.

      The idea here is that the total instruction memory address...