Browse Prior Art Database

Event Triggered Performance Monitoring

IP.com Disclosure Number: IPCOM000113677D
Original Publication Date: 1994-Sep-01
Included in the Prior Art Database: 2005-Mar-27
Document File: 4 page(s) / 130K

Publishing Venue

IBM

Related People

Dwyer, H: AUTHOR [+3]

Abstract

Provide an efficient mechanism to start counting events after another user specified event has occurred without perturbing the state of the machine after the first event occurred and before the counting of the second event is captured.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 45% of the total text.

Event Triggered Performance Monitoring

      Provide an efficient mechanism to start counting events after
another user specified event has occurred without perturbing the
state of the machine after the first event occurred and before the
counting of the second event is captured.

      Using the support defined in (*) and summarized in the
appendix, find a way to take samples of an event only after some
other user specified event has occurred.  Using the previously
defined support, counting of events occurs concurrently.  If you
wanted to see, for example, how many cache misses occurred between
two (2) SYNC instructions, you would need to take an interrupt at the
first SYNC instruction, set the counters appropriately and take
another interrupt at the next SYNC instruction.  The problem with
this approach is that the process of taking the interrupt may
significantly affect the state of the machine.  There are ways to
minimize this effect, such as, making sure that the interrupt routine
is pinned and in write through non-cacheable storage, but there are
costs associated with these approaches.

      The solution would be to define PMCnINTCONTROL fields in the
MMCR0, which disable interrupt signalling due to the PMCn counter
being negative (the condition that usually triggers an interrupt).
This allows the control of the interrupt signalling on an individual
counter basis.

      Define PMCnCOUNTCTL fields in the MMCR0, which disable PMCn, n
> 1, counting until the PMC1 counter is negative or a performance
monitoring interrupt is signalled.  This allows the control of the

PMCn, n > 1, counting as a function of the first counter's state or
as a function of the interrupt signalling.

      With these additional controls, the control of interrupt
signalling and counting is significantly enhanced.

Rationale/expected usage -  In a typical three (3) counter example:
  o  DISCOUNT set to stop counting when the performance monitoring
     interrupt is signalled.
  o  PMC1INTCONTROL set to disable interrupt signalling due to the
     PMC1 counter being negative.
  o  PMC2INTCONTROL set to enable interrupt signalling due to the
PMC2
     counter being negative.
  o  PMC3INTCONTROL set to enable interrupt signalling due to the
PMC3
     counter being negative.
  o  PMC2COUNTCTL set to prohibit the counting of PMC2 until the PMC1
     counter is negative or an interrupt is signalled.
  o  PMC3COUNTCTL set to prohibit the counting of PMC3 until the PMC1
     counter is negative.
  o  PMC1 counter set to go negative after some number of events have
     occurred, say 1000.
  o  PMC2 counter set to go negative after it counted one (1) event
  o  PMC3 counter could be zero.

      In this example, if PMC1 is counting instructions, PMC2 is
counting cache misses, and PMC3 is counting cycles, then the
interrupt would be signalled when the first cache miss occurred after
the 1000th instru...