Browse Prior Art Database

System I/O Bus Read Only Storage Access Mechanism for a Multi-Chip Module Processor

IP.com Disclosure Number: IPCOM000113687D
Original Publication Date: 1994-Sep-01
Included in the Prior Art Database: 2005-Mar-27
Document File: 2 page(s) / 39K

Publishing Venue

IBM

Related People

Feiste, K: AUTHOR [+3]

Abstract

This disclosure provides a scheme to provide a dual usage System I/O (SIO) Bus interface and Read Only Storage (ROS) interface. This removes the need for a dedicated ROS interface out of the processor. As processor chips are packaged onto multi-chip modules the number of I/O signals available for external interfaces has been decreased. Furthermore, it is desirable to reduce the number of external interfaces used by the processor due to cost of drivers/receivers (silicon) and wiring.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 83% of the total text.

System I/O Bus Read Only Storage Access Mechanism for a Multi-Chip
Module Processor

      This disclosure provides a scheme to provide a dual usage
System I/O (SIO) Bus interface and Read Only Storage (ROS) interface.
This removes the need for a dedicated ROS interface out of the
processor.  As processor chips are packaged onto multi-chip modules
the number of I/O signals available for external interfaces has been
decreased.  Furthermore, it is desirable to reduce the number of
external interfaces used by the processor due to cost of
drivers/receivers (silicon) and wiring.

      The ROS interface has been incorporated into the double word
SIO bus signals.  The Storage Control Unit (SCU) chip generates the
ROS address and controls and four Data Cache Unit (DCU) chips receive
the data bus.  A unique feature of this invention is the ability to
send the ROS data to the four DCU chips which are organized such that
each receives only two bytes of the SIO bus.  Thus, the ROS data bus
cannot simply be dotted onto the same byte of the SIO bus.  To solve
the problem of routing the ROS data bus to different bytes of the SIO
bus the SCU receives the ROS data byte on one half of the SIO bus and
latches the data.  The SCU also drives the ROS address and controls
on this same half of the SIO bus.  Thus, the SCU is driving three
bytes of one word of the bus and receiving data on the fourth byte.
On the following cycle the SCU drives the ROS data byte onto all four
bytes of...