Browse Prior Art Database

High Speed Integrated Multi-Bus Memory Sub-System for Personal Computers

IP.com Disclosure Number: IPCOM000113705D
Original Publication Date: 1994-Sep-01
Included in the Prior Art Database: 2005-Mar-27
Document File: 2 page(s) / 94K

Publishing Venue

IBM

Related People

Chan, FL: AUTHOR [+5]

Abstract

Described is an architectural implementation to provide a high-speed integrated multi-bus memory sub-system for Personal Computers (PCs) equipped with a Micro Channel* (MC) so as to increase system operational performance.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 52% of the total text.

High Speed Integrated Multi-Bus Memory Sub-System for Personal Computers

      Described is an architectural implementation to provide a
high-speed integrated multi-bus memory sub-system for Personal
Computers (PCs) equipped with a Micro Channel* (MC) so as to increase
system operational performance.

      Typically, a PC system's memory comprises Dynamic Random Access
Memory (DRAM) and cache memory.  The cache memory uses Static Random
Access Memory (SRAM) devices.  In prior art, a PC memory controller,
designed for DRAM operations, was considered to be too slow in
performance and required cache devices to increase performance.  With
the two memory devices, DRAM and SRAM installed, a memory controller
and a cache, without a dedicated Input/Output (I/O) channel memory
controller, required overhead operations, such as write- back-dumps
and memory cycle bus conversions.  As a result, this additional
overhead affected operational performance.

      The concept described herein is designed to improve operational
performance and to eliminate the involved overhead through the use of
a high speed integrated multi-bus memory sub-system.  The high speed
integrated multi-bus memory sub-system consists of:  1) a Local Bus
(LB) DRAM/SRAM controller for speeding up the Central Processing Unit
(CPU) LB performance; and b) a MC DRAM/SRAM controller to speed up
the MC bus performance.

      The high speed integrated multi-bus memory sub-system is
designed to be sufficiently fast enough for CPU/LB performance so
that no external cache memory is needed.  As a result, the I/O bus,
as in the MC, will not need to slow down for any external cache
write-back-dumps.  Also, the I/O channel performance is increased
through the use of a dedicated memory controller.  As a result, the
I/O bus avoids any bus cycle conversion for an I/O channel memory
access.

      To accomplish this performance improvement, a SRAM controller
is used to work with a DRAM controller on the LB side and a SRAM
controller to work with a DRAM controller on the MC side.  The two
SRAM controllers and the two DRAM controllers work together to make
up the integrated memory sub-system.  In this way, the high speed
integrated m...