Browse Prior Art Database

Off Chip L2 Lateral Cache Miss Counting

IP.com Disclosure Number: IPCOM000113711D
Original Publication Date: 1994-Sep-01
Included in the Prior Art Database: 2005-Mar-27
Document File: 2 page(s) / 94K

Publishing Venue

IBM

Related People

Levine, FE: AUTHOR [+4]

Abstract

Provide a mechanism to allow the processors in an SMP system to distinguish between L2 cache misses that are satisfied directly from main memory and those that are satisfied by a lateral L2 cache.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 52% of the total text.

Off Chip L2 Lateral Cache Miss Counting

      Provide a mechanism to allow the processors in an SMP system to
distinguish between L2 cache misses that are satisfied directly from
main memory and those that are satisfied by a lateral L2 cache.

      A way is needed to count L2 cache misses that are satisfied
from main memory as well as L2 cache misses that are satisfied by
accessing a lateral L2 cache.  This a simple problem when the L2
cache processing is supported directly by the processor.  When the L2
cache controller is off the chip, then there must be a communication
mechanism between the L2 cache controller and the processor to
provide this functionality.  The ability to make this distinction is
especially important, because this information can expedite software
performance tuning.

      Preferred Approach - Define two events to count:  L2 cache
misses satisfied from main memory and l2 cache misses satisfied from
a lateral L2 cache.  Likewise, define a new system-bus pin called
LAT_HIT.  Since the sampling algorithm only requires a randomized
selection, the processor is only required to keep track of exactly
one item to be sampled at a time.  When the selected/sampled load or
store is put on the processor bus, the processor determines whether
there is an L2 cache miss by monitoring the number of cycles to
receive a response.  (This approach can be used to determine if there
is an L1 miss and an L2 hit, but it cannot be used to distinguish
between lateral cache hits and memory hits.  Because the time for an
L2 hit is system dependent, a user selectable time for determining
that there is an L2 hit or miss is recommended to be implemented
along with this support.).  When there is an L2 miss on a sampled
instruction, the processor will increment the lateral hit counter if
LAT_HIT is active during the Transfer Address (TA) system-bus phase
of the data transfer.  If there is an L2 miss on a sampled
instruction and the LAT_HIT is not active during the TA system-bus
phase of the data transfer, then the processor will increment the L2
cache miss satisfied from main memory counter.

      The above approach works on PowerPC* systems with external L2
cache controllers and is easy to implement.  The reason is that if a
processor snoops an access on the system-bus and drives out MODIFIED,
then that processor will provide data for another processor's read.
(It can reply RETRY and then push the data to memory, the reading
processor will subseq...