Browse Prior Art Database

Programmable Scrambler/Descrambler

IP.com Disclosure Number: IPCOM000113718D
Original Publication Date: 1994-Sep-01
Included in the Prior Art Database: 2005-Mar-27
Document File: 2 page(s) / 61K

Publishing Venue

IBM

Related People

Andrews, LP: AUTHOR [+4]

Abstract

Disclosed is a circuit and method which performs the scrambling and descrambling of baseband binary data. The context of the circuit can be saved and restored to allow the use of a single hardware circuit to support many modem channels processed by a single Digital Signal Processor (DSP) chip. Thus, the context is switchable for many channels, as scrambling and descrambling are achieved through the use of programmable polynomials and a programmable shift count.

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This is the abbreviated version, containing approximately 63% of the total text.

Programmable Scrambler/Descrambler

      Disclosed is a circuit and method which performs the scrambling
and descrambling of baseband binary data.  The context of the circuit
can be saved and restored to allow the use of a single hardware
circuit to support many modem channels processed by a single Digital
Signal Processor (DSP) chip.  Thus, the context is switchable for
many channels, as scrambling and descrambling are achieved through
the use of programmable polynomials and a programmable shift count.

      The scrambler/descrambler implements the CCITT V.29, V.32, and
V.32 bis polynomial (*).  The polynomials used are the Call Mode
Generating Polynomial (GPC), given by Equation 1) and the Answer Mode
Generating Polynomial, given by Equation 2).

      The Figure is a block diagram of the scrambler/descrambler.
This logic performs scrambling or descrambling based on the selection
of an input to XOR gate 10.  The Boolean equations for the outputs
are Data Scrambled (Ds), given by Equation 3), and Data Descrambled
for Answer Mode (Do), given by Equation 4).  This logic is context
sensitive; to save the context, the contents of a status register 11
associated with an F.S.M.  (Finite State Machine) 12, the input byte
in input register 13, and the contents of the 24-bit shift register
14 are saved.

      This circuit is programmable for either an Answer or Originate
Mode, and for either scrambling or descrambling.  Also, the context
of the circuit can...