Browse Prior Art Database

Decoupling Circuit Structure to Reduce Electrical Noise

IP.com Disclosure Number: IPCOM000113722D
Original Publication Date: 1994-Sep-01
Included in the Prior Art Database: 2005-Mar-27
Document File: 2 page(s) / 59K

Publishing Venue

IBM

Related People

Cases, M: AUTHOR [+4]

Abstract

Described is a hardware implementation to provide an on-chip decoupling capacitance structure for Very Large Scale Integrated (VLSI) circuits. The implementation is designed to reduce internally induced electrical noise without impacting the size of the circuit chip.

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This is the abbreviated version, containing approximately 68% of the total text.

Decoupling Circuit Structure to Reduce Electrical Noise

      Described is a hardware implementation to provide an on-chip
decoupling capacitance structure for Very Large Scale Integrated
(VLSI) circuits.  The implementation is designed to reduce internally
induced electrical noise without impacting the size of the circuit
chip.

      Typically, VLSI circuitry contains a Central Processing Unit
(CPU) and associated controller units using process technologies that
produced fast signal transitions.  As faster signal transitions and
larger numbers of simultaneous switching of drivers during clock
cycles take place, excessive electrical noise becomes evident.
Generally, the internally created electrical noise can be reduced by
increasing the number of power pins, including ground pins, at the
first level of packaging.  This effectively reduces the pin
inductance, thereby, reducing the power supply and signal noise.
Additionally, plastic packages and other related forms of integrated
chip packages have enabled chip designers to explore other means of
reducing the internal electrical noise.

      The concept described herein provides a means of reducing
internal electrical noise on VLSI chips by incorporating an
integrated decoupling capacitance structure within the chip circuitry
with minimum impact to wiring congestion and chip density.  The
structure is designed for use in the logic core of the chip as well
as for use with the Input/Output (I/O) ring associat...