Browse Prior Art Database

Swapping Failing Bits in 40-Pin Error Correcting SIMMS

IP.com Disclosure Number: IPCOM000113723D
Original Publication Date: 1994-Sep-01
Included in the Prior Art Database: 2005-Mar-27
Document File: 2 page(s) / 81K

Publishing Venue

IBM

Related People

Aldereguia, A: AUTHOR [+3]

Abstract

Disclosed is a method for handling hard single-bit errors in SIMM memory modules with an Error Correcting Code (ECC) feature, allowing a computing system to continue operating without sacrificing soft error detecting and correction capability. The failing bit location is remapped to an unused bit. Many systems use a 40-bit SIMM module for a 32/7 ECC algorithm. Since 32 bits are required for data, along with 7 check bits, there is a single unused bit, which provides an extra bit to be swapped with a failing data bit.

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Swapping Failing Bits in 40-Pin Error Correcting SIMMS

      Disclosed is a method for handling hard single-bit errors in
SIMM memory modules with an Error Correcting Code (ECC) feature,
allowing a computing system to continue operating without sacrificing
soft error detecting and correction capability.  The failing bit
location is remapped to an unused bit.  Many systems use a 40-bit
SIMM module for a 32/7 ECC algorithm.  Since 32 bits are required for
data, along with 7 check bits, there is a single unused bit, which
provides an extra bit to be swapped with a failing data bit.

      Without the implementation of this method, when a computing
system detects excessive single-bit errors during Power-On Self-Test
(POST), an error message is issued to the system user, who can either
proceed to start the operating system or run diagnostics to determine
the nature of the problem.  If the problem is isolated to a single
SIMM module, that module is disabled, allowing the system to run with
less memory.  If the problem affects several SIMMs, or if the user
cannot run with less memory, the system operates with the single-bit
failure problem until it is serviced.

      With the implementation of this method, when POST or
diagnostics detects a hard-bit failure or excessive single-bit
failures, the failing bit is identified by the syndrome bits of the
ECC.  Software selects the bit to be swapped and enables the swap
mode.  When this mode is enabled, memory does not have to be
initialized again, although each location in memory should be
scrubbed by being first read and then written.  When the location of
the failing bit is read, the data is written on Bit 39.  After memory
is written, the error is eliminated, since the failing bit has been
replaced by Bit 39.

      The Figure is a block diagram showing the an enhanced...