Browse Prior Art Database

Channel Read Only Memory Cacheability for Personal Computers

IP.com Disclosure Number: IPCOM000113737D
Original Publication Date: 1994-Sep-01
Included in the Prior Art Database: 2005-Mar-27
Document File: 4 page(s) / 147K

Publishing Venue

IBM

Related People

Bland, PM: AUTHOR [+3]

Abstract

Described is a circuit logic implementation to provide a means of mapping channel-adapter Read Only Memory (ROM) code into a cache processor, as used in Personal Computers (PCs). The primary objective of the implementation is to minimize the number of circuit gates and to maximize the usage of existing cacheability control signals.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 52% of the total text.

Channel Read Only Memory Cacheability for Personal Computers

      Described is a circuit logic implementation to provide a means
of mapping channel-adapter Read Only Memory (ROM) code into a cache
processor, as used in Personal Computers (PCs).  The primary
objective
of the implementation is to minimize the number of circuit gates and
to
maximize the usage of existing cacheability control signals.

      In prior art, PCs with a main memory address region of
768k-896k (C0000h-DFFFFh) had this region unconditionally
non-cacheable and reserved for a remap of adapter card ROM code.  The
performance of some applications using certain channel adapters was
improved by making the region where the code was remapped cacheable,
such as putting the code in the level one cache.  This region was
split into sixteen blocks of 8k each with a separate control bit
indicating whether it was cacheable or non-cacheable.  An adapter
card was assigned to one or more of these blocks.

      The concept described herein deals with an optimal way of
determining whether an incoming address falls into one of the sixteen
regions and if so, whether the adapter code mapped to that region is
programmed to be cacheable or non-cacheable.  The implementation is
optimized using pre-existing signals available for cacheability
determinations in other memory regions.

      The first step in implementing the cacheability function is
isolating which address bits are unique in the determination of
whether the incoming address is within one of the sixteen ranges.  In
systems where addresses above 256 megabytes are not supported,
address bits 31 through 28 (ADDR(31:28)) must always be zero, or an
error condition would be flagged at a higher level in the design
hierarchy.  This implies that these bits need not be examined to
implement this function.  ADDR(27:20) must also all be zero or the
address would be above the top of the range, or greater than
000DFFFFh.  These bits must therefore be tested to be certain that
they are all equal to zero.   A signal already exists in the system
to indicate this is true for other cacheability functions and is
labelled A2027EQ0 in the schematic Figure.  If this signal is a one,
one or more of these bits are not equal to zero.  Therefore, the
output is disabled by means of NOR gates C and A and invertor Z.  If
this signal is a zero, the output may be enabled, but further
decoding is necessary on the incoming address.  The next group of
bits of interest are ADDR(19:16).  There are only two combinations
that are valid within the range of interest, hex 'C' and 'D' (1100
and 1101 binary, respectively).  By inspection, ADDR(19:17) must
always be binary 110.  The implementation of this function is with
NAND gate D...