Browse Prior Art Database

Multiple Bus System with Variable Bus Speed and Bus Width

IP.com Disclosure Number: IPCOM000113740D
Original Publication Date: 1994-Sep-01
Included in the Prior Art Database: 2005-Mar-27
Document File: 4 page(s) / 167K

Publishing Venue

IBM

Related People

Feiste, K: AUTHOR [+4]

Abstract

Disclosed is a method for controlling a computer system with multiple internal buses which may run at different clock speeds and have different bus widths.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 46% of the total text.

Multiple Bus System with Variable Bus Speed and Bus Width

      Disclosed is a method for controlling a computer system with
multiple internal buses which may run at different clock speeds and
have different bus widths.

      A common technique used to transfer data in a computer system
is to combine a group of signals together and pass the information in
parallel over a bus.  The buses in the system may have different
physical characteristics due to bus loading, wire distance, as well
as the components attached to a given bus.  In the past, the clock
speed that the CPU chips could run was limited by the speed that the
bus interfaces between the chips could be run at.  This invention
describes a method of controlling a computer system which has
multiple internal data buses which may have different bus clock
speeds and different bus widths.  In this scheme the system is not
limited by the speed of the external buses because they can be
programmed to run at half the CPU clock speed.  In addition, only the
chips which interface to the slower buses must be synchronized to the
multiple bus speeds.  It is transparent to the other chips that the
external buses are running slower.

      Fig. 1 shows a system diagram consisting of a multi-chip
super-scalar RISC CPU, L2 cache, memory, and I/O control units.  The
CPU consists of an Instruction Cache Unit (ICU), a Fixed Point Unit
(FXU), a Floating Point Unit (FPU), four Data Cache Units (DCU), and
a Storage Control Unit (SCU).  An external Clock Chip (CLK) generates
bus phase signals for the memory bus and the SIO bus for half-speed
mode.  The buses of interest in this configuration are the Processor
Bus (PBUS) which is a single word bus that always runs at full speed,
the double word System I/O (SIO) bus which can run at full speed or
half speed, the memory data bus which can run with 2 or 4 words and
run at full or half speed, and the L2 Cache data bus which can run
with 2 or 4 words and runs at full speed.  Many of the operations
which occur in the system use a combination of these four buses.  In
this scheme only the SCU and DCU must synchronize to the slower SIO
and memory bus.  It is transparent to the ICU, FPU, and FXU that
these buses are running at half speed.

      Main memory operations use the PBUS, the memory data bus, and
the L2 data bus.  The memory bus and the L2 data bus can be
configured to be either 2 words or 4 words.  In addition, the memory
bus can be programmed to run in full or half-speed mode.  Memory
operations are initiated from the FXU or ICU over the PBUS which runs
at full speed.  Cache lines are loaded and stored from memory in
either full or half speed and returned to the CPU Level 1 (L1) caches
as well as the L2 cache which runs at full speed.   Fig. 2 shows a
timing diagram of an ICache reload from memory at half the CPU clock
speed.  As seen in Fig. 2, the memory D-Clock is half the speed of
the CPU clock speed.  A memory bus pha...