Browse Prior Art Database

Dynamic Random Access Memory Data Burst Control

IP.com Disclosure Number: IPCOM000113742D
Original Publication Date: 1994-Sep-01
Included in the Prior Art Database: 2005-Mar-27
Document File: 6 page(s) / 258K

Publishing Venue

IBM

Related People

Busch, RE: AUTHOR [+5]

Abstract

A method to control sequential or interleaved data being written into or read from Dynamic Random Access Memory (DRAM) modules is disclosed. The sequential or interleaved data in this disclosure is refered to as a data burst, one or more data bits in length. Advanced applications for DRAMs require quick access times and high data rates. This method achieves an improvement in data rate by dynamically adjusting the length of the data burst, using the high logic level of an input signal named BC or Burst Control. A low logic level on the BC input allows data bursts to end at a predetermined default length of 4 or 8 data bits. A high logic level on the BC input ends data bursts, allowing a new burst to be started sooner.

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This is the abbreviated version, containing approximately 26% of the total text.

Dynamic Random Access Memory Data Burst Control

      A method to control sequential or interleaved data being
written into or read from Dynamic Random Access Memory (DRAM) modules
is disclosed.  The sequential or interleaved data in this disclosure
is refered to as a data burst, one or more data bits in length.
Advanced applications for DRAMs require quick access times and high
data rates.  This method achieves an improvement in data rate by
dynamically adjusting the length of the data burst, using the high
logic level of an input signal named BC or Burst Control.  A low
logic level on the BC input allows data bursts to end at a
predetermined default length of 4 or 8 data bits.  A high logic level
on the BC input ends data bursts, allowing a new burst to be started
sooner.  By terminating an existing data burst after the required
data is transfered and beginning a new data burst in a dynamic
manner, more of the required data is tranfered in a given interval of
time.  This method is particularly applicable to DRAMs that have
multiple memory array banks (partitions that are independantly
accessed) and operate asyncronously in an interleaved manner.

      A brief review of some advanced DRAM applications is helpful in
introducing an embodiment of the Burst Control signal.  1) Many
existing DRAMs are used in a Page Mode operation where data is
tranfered into or out of the DRAM with the Column Address Strobe
clock signal (CAS, with an overscore, or CAS\).  One bit of data is
transfered for every CAS\ cycle.  2) A variation on Page Mode is
Nibble Mode, where addresses do not need to change for every CAS\
signal but there is still only one data bit for every CAS\ cycle.  3)
A further data rate improvement is achieved by using an input clock
signal named Toggle or TOG.  The TOG signal transfers data on every
rising as well as falling transition, approximately doubling the data
rate over Page Mode.  Addresses need only change for every other bit
of data.  4) Another improvement in data rate is achieved with
Synchronous DRAM or SDRAM, where data is transfered at the rising
edge of a continuously running clock signal.  The column address is
selected one or more clock signals prior to transfering data out of
the SDRAM, and a total of 1, 2, 4, 8, or more data bits are
transfered in conjuction with that particular Column Address.  The
transfer length is called the Burst Length.  5) The following
embodiment using the Burst Control and TOG signals together offers a
data rate comparable to that of SDRAM.  When using the Burst Control
and TOG signals, the continuously running clock signal of the SDRAM
is not required.
  The Burst Control embodiment is best described using block
  diagrams and signal timing charts.

      Fig. 1 shows a block diagram of an output circuit of a DRAM to
illustrate the operation of the CAS\, TOG and BC signals in
generating and controlling data bursts during read cycles.  Not shown
is how data is...