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High Speed Design for Dynamically Aligning Data in a Multi Byte Bus System

IP.com Disclosure Number: IPCOM000113746D
Original Publication Date: 1994-Sep-01
Included in the Prior Art Database: 2005-Mar-27
Document File: 6 page(s) / 200K

Publishing Venue

IBM

Related People

Bass, BM: AUTHOR [+5]

Abstract

Described is a method which solves a problem that can be found in many areas of logic design. This is how to efficiently shift the position of a string of data in memory on a byte by byte basis. For example, you have a 20 byte string of data that starts on byte 3 of a given word of memory and the next stage of the design actually requires that it starts on byte 1 of the design. This is not a trivial problem to solve when the starting and ending positions for the data can change dynamically. The solution provided here allows the output data to be available during the same cycle as the input data in most cases, and is, therefore, the most efficient solution to this problem.

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High Speed Design for Dynamically Aligning Data in a Multi Byte Bus
System

      Described is a method which solves a problem that can be found
in many areas of logic design.  This is how to efficiently shift the
position of a string of data in memory on a byte by byte basis.  For
example, you have a 20 byte string of data that starts on byte 3 of a
given word of memory and the next stage of the design actually
requires that it starts on byte 1 of the design.  This is not a
trivial problem to solve when the starting and ending positions for
the data can change dynamically.  The solution provided here allows
the output data to be available during the same cycle as the input
data in most cases, and is, therefore, the most efficient solution to
this problem.

      The key idea of this design is that the output data is built a
word at a time as the data is being read from the internal buffer.
The data is built using a combination of the data read from the
internal buffer on the current cycle and the data that was read and
not used to build the output data word on the previous cycle.  This
allows the newly created data word to be placed on the output bus on
the same cycle that it is read from the internal data buffer.  Fig. 1
illustrates how the alignment logic interfaces to the outside world
to create the desired function.

The following list describes the signals used in the Fig. 1 to
control the alignment logic.
  o  clock (input) - System clock.
  o  txstrobe (input) - Indicates data is available on the input data
     bus and is ready to be aligned.
  o  input data (input) - Input data bus (data = trd, data parity =
     trdp, byte enables = trbe).
  o  txoff (input) - Starting byte position for the output data.
This
     is an encoded signal.  Therefore, for a 4 byte wide bus this
will
     be a 2 bit signal.
  o  txalign (input) - Indicates that the current word is the first
     word of a packet.
  o  txagain (output) - Indicates that the first word was not enough
     to create an output data word, and to transmit a second word.
  o  dataheld (output) - Indicates that there is still valid data in
     the held data register.  When this signal is active, the
outbound
     data control logic will need to activate the txstrobe signal
     again with dummy data on the input data bus to drive the last
     word onto the output data bus.
  o  output data (output) Output data bus (data = outd, data parity =
     outdp, byte enables = outbe).
  o  outstrobe (output) - Signal indicating that the data going to
the
     output data bus is valid.
     data bus.

      In Fig. 2, the flow of data is from the input data bus to the
output data bus.  When data arrives on the input data bus it is
either saved or passed onto the MUX.  The decode logic is used to
save the appropriate bytes for use in the next output data word.  The
MUX is used to control the buildi...