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Low Output Impedance DC/DC Converter

IP.com Disclosure Number: IPCOM000113747D
Original Publication Date: 1994-Sep-01
Included in the Prior Art Database: 2005-Mar-27
Document File: 4 page(s) / 129K

Publishing Venue

IBM

Related People

Johari, GC: AUTHOR [+2]

Abstract

A modern computer system utilizing CMOS technology presents highly dynamic loads to the power system. It is common for portions of the system to switch from ten percent load to full load in a few microseconds. this load behavior makes it difficult to keep the power bus voltages in regulation. Large decoupling capacitors at the load partially solve the problem, however at low bus voltages, the amount of decoupling required can become unmanageable. For example, at a given power level, 4 times as much decoupling is required to keep a 2.5V bus within a specified percentage tolerance as for a 5V bus. Electrolytic capacitor impedance is dominated by equivalent series resistance and inductance at high frequencies, and these parameters are determined mostly by case size, independent of the voltage rating of the capacitor.

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Low Output Impedance DC/DC Converter

      A modern computer system utilizing CMOS technology presents
highly dynamic loads to the power system.  It is common for portions
of the system to switch from ten percent load to full load in a few
microseconds.  this load behavior makes it difficult to keep the
power bus voltages in regulation.  Large decoupling capacitors at the
load partially solve the problem, however at low bus voltages, the
amount of decoupling required can become unmanageable.  For example,
at a given power level, 4 times as much decoupling is required to
keep a 2.5V bus within a specified percentage tolerance as for a 5V
bus.  Electrolytic capacitor impedance is dominated by equivalent
series resistance and inductance at high frequencies, and these
parameters are determined mostly by case size, independent of the
voltage rating of the capacitor.  Therefore 4 times as much space
must be devoted to decoupling at the lower voltage as at the higher
voltage.  This problem may be alleviated by putting most of the
decoupling at an intermediate, higher voltage level and coupling it
to the load through a DC/DC converter with very low input to output
impedance.  A 2.5V to 20V conversion ratio would represent a 64 fold
reduction in decoupling capacitor volume, a significant improvement.

      To achieve the best possible coupling between the intermediate
capacitors and the load, the DC/DC converter should run at nearly
full duty cycle and have minimal inductance in the high current
paths.  Since a full duty cycle DC/DC converter cannot provide
voltage regulation, (it acts essentially as a dc transformer), a
DC/DC preregulator is required to sense the load voltage and adjust
the voltage level on the intermediate capacitors to compensate for
variations in input voltage, component drift, and long term load
changes.  Fig. 1 shows the complete circuit in block diagram form.

      While the design of the DC/DC preregulator is straightforward,
the low impedance DC/DC converter design presents some challenges.
Full wave single transformer topologies, such as the push pull, half
bridge or full bridge, require perfect volt time balance between the
halves of the operating cycle to keep magnetic flux centered.  If
balance is not maintained, the transformer core can saturate, causing
failure of the converter.  The commonly used method of core balancing
a push pull or full bridge converter, current mode control, is
undesirable because it requires current sensing, feedback control,
and dead time adjustment, all of which indirectly increase impedance.
The half bridge topology does not require external flux balancing,
but the capacitor divider circuit at the input adds impedance and
greatly increases the size of the converter.  Single ended designs
using one power train require long dead times to reset the
transformer core, necessitating substantial output filtering
resulting in high impedance.

      PROPOSED CIRCUIT AND...