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Memory Sharing in Parallel Processing Environments

IP.com Disclosure Number: IPCOM000113757D
Original Publication Date: 1994-Sep-01
Included in the Prior Art Database: 2005-Mar-27
Document File: 4 page(s) / 177K

Publishing Venue

IBM

Related People

Klenk, K: AUTHOR

Abstract

Described is an object-oriented method to access a memory and its combination with an atomic test and lock operation on the object. The access processing is handled by Access Control Units (ACU). An ACU receives an Object-Oriented Conditional Access Request (OCAR), prepares a conditional access to memory and handles the response of this request. The conditional access includes the atomic test-and-lock of the addressed object. Depending on the type of object the ACU performs all subsequent operations to handle update of control data, data transfer etc.

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Memory Sharing in Parallel Processing Environments

      Described is an object-oriented method to access a memory and
its combination with an atomic test and lock operation on the object.
The access processing is handled by Access Control Units (ACU).  An
ACU receives an Object-Oriented Conditional Access Request (OCAR),
prepares a conditional access to memory and handles the response of
this request.  The conditional access includes the atomic
test-and-lock of the addressed object.  Depending on the type of
object the ACU performs all subsequent operations to handle update of
control data, data transfer etc.

Object-oriented Conditional Access Technique (OCAT)
  1.  OCAT Description

      The idea is explained on elements of the IBM S/390 architecture
but it is not restricted to that architeture.

      Current IBM S/390* implementations are tightly-coupled CPUs
which share one single memory.  The same memory can also be accessed
from I/O processors.  The I/O processors are allowed to access
certain memory locations per convention and as defined in channel
commands.  The channel commands are used as orders for the I/O
processors to transfer data to or from memory.  I/O processors can be
signaled from CPUs and they can respond with signals.  If an I/O
processor is signalled from a CPU, it reads some control data which
point to the channel program.  The channel program consists of
channel commands, and each channel command is an order for the I/O
processor.

      CPUs perform memory access through caches to load, compute or
store data.  Access is unconditional and does not care about the
structure of data.  The form of an object is not known by cache
management.

      If two or more users want to access the same object, they use
some part of that object as lock-byte, -word or -double word.
Manipulation is only allowed with the test-and-set or
compare-and-swap instructions to make sure, that test and update
happen in one noninteruptiple (atomic) cycle.  Subsequent
manipulation of control data is controlled through the CPU.  If the
control data are updated, the responsible CPU updates the user data
and unlocks the semaphore which coordinates the access.

      CPUs which can access memory directly, are called local CPUs,
others are remote CPUs.  Operations as explained above can only be
performed from locally attached CPUs today.  If a remote CPU wants to
access such a shared object, it must ask a local CPU to perform the
access for it and to initialize the transfer of the result in form of
data and/or control messages.

      A set of CPUs and the main storage is called a Central
Electronics Complex (CEC).  In a Parallel Processing Environment a
number of those CECs is combined in a cluster and memory must be
shared among the CECs.  Memory sharing requires an enormous
administrative effort today.  The intention of the presented idea is
to minimize this administrative effort by proposing a diff...