Browse Prior Art Database

Initial Microcode Load Overlay Execution for Personal Computers

IP.com Disclosure Number: IPCOM000113762D
Original Publication Date: 1994-Oct-01
Included in the Prior Art Database: 2005-Mar-27
Document File: 4 page(s) / 178K

Publishing Venue

IBM

Related People

Dunham, S: AUTHOR [+5]

Abstract

Described is an architectural implementation to resolve code space restrictions inherent in certain Personal Computers (PCs). Power-On System Test (POST) and Initial Microcode Load (IML) overlays are incorporated so as to execute different sections of the POST code, thereby resolving code space restrictions.

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This is the abbreviated version, containing approximately 45% of the total text.

Initial Microcode Load Overlay Execution for Personal Computers

      Described is an architectural implementation to resolve code
space restrictions inherent in certain Personal Computers (PCs).
Power-On System Test (POST) and Initial Microcode Load (IML) overlays
are incorporated so as to execute different sections of the POST
code, thereby resolving code space restrictions.

      Due to the increasing functional requirements of PCs, such as
the IBM PS/2* computers, a corresponding increase has resulted in the
amount of code necessary to test and to initialize POST operations.
Typically, the 128K byte area, where POST and the Basic Input/Output
System (BIOS) code resided, was limited restricting the usage of
additional POST code.  To overcome this limitation, the concept
incorporates pre-assembled, pre- linked sections of code overlays on
the IML media to enable the incorporation of the increasing
functional requirements.  The overlays do not occupy memory at the
same time, but are serially executed, thereby saving code space.

      In the case of the PS/2, during initial POST IML operations,
E000 and F000 shadow Random Access Memory (RAM) segments with a
portion of the required POST code and all of the required BIOS
code.  The remaining POST code is stored on the media in
pre-assembled-and-linked IML overlays.  These POST overlays are
executed, as required, by being loaded into a 16KB overlay section of
the 128K POST/BIOS area.  Fig. 1 shows a block diagram of the F000
segment RAM POST/BIOS memory map.  During the first IML, the IML
overlays are loaded into RAM, in a low memory address area, to be
stored for use later in the POST operation.  When an overlay is
required, it may be retrieved from the low RAM storage location, or
it can be copied from the media.  Fig. 2 shows a block diagram of the
initial IML media transfers.

      Each overlay contains a overlay identification (ID) field,
model/sub-model byte/revision level field, a date field, and a
check-sum byte.  The ID and the check-sum of an overlay are verified
prior to their execution.  The other fields are used by the
backup/restore and update utilities.  Fig. 3 shows a block diagram of
an overlay structure.

      The routine in control of the loading and execution of the
overlays is called the "Loader" routine.  This routine calls the
first overlay and upon return determines the next required overlay by
searching an overlay ID table which lists the sequence of the overlay
execution.  The Loader checks a flag which indicates whether the
overlay can be loaded from RAM, or whether it should be copied from
the IML media.  This flag is set to indicate that the overlay is
available in RAM until the execution of the adapter's POST, since it
is possible that the adapter's POST may potentially corrupt the
overlays stored in RAM.  After the adapter POST operation, the flag
is set to indicate that the overlays must be retrieved from the
media.  If an...