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Restructured Serial Port Clock with Double Baud Rate

IP.com Disclosure Number: IPCOM000113776D
Original Publication Date: 1994-Oct-01
Included in the Prior Art Database: 2005-Mar-27
Document File: 2 page(s) / 49K

Publishing Venue

IBM

Related People

Lam, SH: AUTHOR

Abstract

Disclosed is a method for restructuring the clock of a serial port in such a way that the baud rate divisor can be programmed to divide by one at a high baud rate. This method allows transmission, which was previously limited to 345 kb (kilobaud), to occur at 690kb (kilobaud).

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Restructured Serial Port Clock with Double Baud Rate

      Disclosed is a method for restructuring the clock of a serial
port in such a way that the baud rate divisor can be programmed to
divide by one at a high baud rate.  This method allows transmission,
which was previously limited to 345 kb (kilobaud), to occur at 690kb
(kilobaud).

      Fig. 1 is a block diagram of the previous serial port clock, in
which the clock frequency is divided by two at a division circuit 10
to provide clock inputs to a baud rate generator 12, and divisor
register 14, and the remaining circuits 16 on a circuit chip.  With
this circuit, if the divisor register 14 is programmed to a value of
"one," indicating that division by one is desired, the BAUDOUT signal
from the baud rate generator 12 and the CLK2 signal, which are both
applied as inputs to remaining circuits 16, are the same signals.
Under this condition, remaining circuits 16 do not function properly.

      Fig. 2 is a block diagram of a serial port clock to which the
presently disclosed method has been applied, with the undivided clock
frequency being provided as a clock input to divisor register 14 and
to remaining circuits 16.  Only baud rate generator 12 is clocked
with the divided frequency.  In this way, if divisor register 14 is
programmed to a value of "one," the BAUDOUT and CLK signals applied
as inputs to remaining circuits 16 are not the same signals, so
remaining circuits 16 function properly.