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Complementary Metal Oxide Semiconductor Source Terminated Driver DI/Dt Control Method

IP.com Disclosure Number: IPCOM000113780D
Original Publication Date: 1994-Oct-01
Included in the Prior Art Database: 2005-Mar-27
Document File: 2 page(s) / 40K

Publishing Venue

IBM

Related People

Dreps, DM: AUTHOR [+3]

Abstract

Implementation of the method described minimizes the effect of di/dt variation which causes limitation of the number of drivers that can be switched at one time in CMOS Off-Chip Driver (OCD) technology. Input/Output (I/O) driver output impedance variation can be reduced from 3x to 2x and di/dt variation 4x-5x to about 2.5x. This results in decreased L(di/dt) noise and closer impedance matching to a driven transmission line thereby improving the simultaneous switch factor for a given package and reducing worst-case driver delay. The improvement is accomplished without off-chip components, dissipation of power in the I/O drivers themselves, or feedback from driver outputs to a predrive.

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Complementary Metal Oxide Semiconductor Source Terminated Driver
DI/Dt Control Method

      Implementation of the method described minimizes the effect of
di/dt variation which causes limitation of the number of drivers that
can be switched at one time in CMOS Off-Chip Driver (OCD) technology.
Input/Output (I/O) driver output impedance variation can be reduced
from 3x to 2x and di/dt variation 4x-5x to about 2.5x.  This results
in decreased L(di/dt) noise and closer impedance matching to a driven
transmission line thereby improving the simultaneous switch factor
for a given package and reducing worst-case driver delay.  The
improvement is accomplished without off-chip components, dissipation
of power in the I/O drivers themselves, or feedback from driver
outputs to a predrive.

      The method is basically comprised of one or more on-chip FET
channel length monitor circuits and two sets of current mirrors.
Channel length variation is the main process variable affecting
driver output impedance.  Each monitor circuit sets up contention
currents based on long-channel FETs fighting short-channel FETs.  The
monitor circuit does draw DC current and is equipped to have DC
current shut off during leakage tests.  Two sets of current mirrors
are designed by device width scaling to create "nominal" and "worst
case" cross-over points.  Signals from the mirrors are used to create
control signals which are bussed to the I/O drivers, where they
control predrive current.