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Special Serialization for "Load-with-Update" Instruction to Reduce the Complexity of Register Renaming Circuitry

IP.com Disclosure Number: IPCOM000113784D
Original Publication Date: 1994-Oct-01
Included in the Prior Art Database: 2005-Mar-27
Document File: 2 page(s) / 70K

Publishing Venue

IBM

Related People

Kau, CC: AUTHOR

Abstract

Register renaming is essential to achieve out-of-order execution, and several schemes have been proposed to do it. One scheme is to allocate rename buffers to the target registers of every instruction. In IBM POWER architecture, all fixed-point instructions have one or no target register, except the "load-with-update" class of instructions which two target registers, one for memory data and the other one for the updated effective address. Due to the presence of this class of instructions, N-issue superscalar processor could have up to 2N target registers needed to be renamed simultaneously. The implementation of a priority circuit to handle all these requests becomes a major design challenge when N is large and cycle time is short.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 57% of the total text.

Special Serialization for "Load-with-Update" Instruction to Reduce
the Complexity of Register Renaming Circuitry

      Register renaming is essential to achieve out-of-order
execution, and several schemes have been proposed to do it.  One
scheme is to allocate rename buffers to the target registers of every
instruction.  In IBM POWER architecture, all fixed-point instructions
have one or no target register, except the "load-with-update" class
of instructions which two target registers, one for memory data and
the other one for the updated effective address.  Due to the presence
of this class of instructions, N-issue superscalar processor could
have up to 2N target registers needed to be renamed simultaneously.
The implementation of a priority circuit to handle all these requests
becomes a major design challenge when N is large and cycle time is
short.  The complexity of the priority circuit is directly
proportional to the square of the number of rename requests which is
2N for a N-issue processor.  In a high degree superscalar processor,
this priority circuit is very likely to be the critical path.

      In this invention, a scheme is developed to reduce the
complexity of this circuit.  Since "load-with-update" is the only
class of instructions that have two target registers, a new
serialization scheme is invented to handle this problem.  Under the
new serialization scheme, a "load-with-update" instruction will be
dispatched with only the first target regist...