Browse Prior Art Database

Processor Prefetch Unit with Alternate Path for Transfer Instructions

IP.com Disclosure Number: IPCOM000113787D
Original Publication Date: 1994-Oct-01
Included in the Prior Art Database: 2005-Mar-27
Document File: 2 page(s) / 98K

Publishing Venue

IBM

Related People

Huynh, DQ: AUTHOR [+2]

Abstract

Disclosed is a method for prefetching codes in a processor unit from both a current execution path and an alternative path. The execution of processor instructions generally occurs in a sequential fashion until a transfer instruction, such as a JUMP, BRANCH, or LOOP, is encountered. When a transfer instruction is executed, the execution of instructions either continues along the sequential path, if the condition of the transfer instruction is false, or proceeds to an instruction to which the transfer address points, if the condition of the transfer instruction is true. The method disclosed herein reduces the degradation in system performance occurring when the condition of a transfer instruction is true.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 52% of the total text.

Processor Prefetch Unit with Alternate Path for Transfer Instructions

      Disclosed is a method for prefetching codes in a processor unit
from both a current execution path and an alternative path.  The
execution of processor instructions generally occurs in a sequential
fashion until a transfer instruction, such as a JUMP, BRANCH, or
LOOP, is encountered.  When a transfer instruction is executed, the
execution of instructions either continues along the sequential path,
if the condition of the transfer instruction is false, or proceeds to
an instruction to which the transfer address points, if the condition
of the transfer instruction is true.     The method disclosed herein
reduces the degradation in system performance occurring when the
condition of a transfer instruction is true.  While this method may
be applied to any processor including an instruction prefetch unit,
the application of this method to the Intel i486* microprocessor is
described as an example.

      The i486 microprocessor is characterized by a pipelined
architecture.  The processor consists of nine functional units,
including the BIU (Bus Interface Unit), cache, the IPU (Instruction
Prefetch Unit), and the instruction decode, all of which operate in
parallel.  The BIU interfaces the processor to the system, performing
all bus operations generated by either the Execution Unit (EU) or the
IPU.  The purpose of the IPU is to maintain the instruction stream
supplied to the EU under most circumstances.  This is done by
fetching ahead instructions from either the primary (internal) cache,
the secondary cache, or system memory.  Code prefetches are passed to
both the IPU and to the internal cache.

      Traditionally, the logical instructions are stored sequentially
in the 32-byte prefetch queue.  In other words, the prefetch code is
read from consecutive locations following the instruction to which
the CS:IP instruction pointer points, regardless of the nature of the
instructions.  As a result, when the condition of a transfer
instruction is true, all instructions in the prefetch unit must be
flushed and replaced with sequential instructions beginning with the
instruction to which the transfer address points.  The overhead in
refilling the prefetch queue forces the EU to wait, resulting in the
degradation of system performance, especially when the subsequent...