Browse Prior Art Database

Fast Propogation Complementary Metal Oxide Semiconductor LSSD Latch

IP.com Disclosure Number: IPCOM000113793D
Original Publication Date: 1994-Oct-01
Included in the Prior Art Database: 2005-Mar-27
Document File: 2 page(s) / 47K

Publishing Venue

IBM

Related People

Gregor, RP: AUTHOR [+3]

Abstract

A new CMOS LSSD latch is designed to maintain simplicity of circuit design while maintaining minimum and symmetric delay for set and reset operation. This is accomplished by using a pair of NFETs on the true and complement nodes of the latch, one gated by "Data True" and the other by "Data Complement", to differentially set or reset the latch state. There is no additional clock loading due to the new design.

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Fast Propogation Complementary Metal Oxide Semiconductor LSSD Latch

      A new CMOS LSSD latch is designed to maintain simplicity of
circuit design while maintaining minimum and symmetric delay for set
and reset operation.  This is accomplished by using a pair of NFETs
on the true and complement nodes of the latch, one gated by "Data
True" and the other by "Data Complement", to differentially set or
reset the latch state.  There is no additional clock loading due to
the new design.

        The simplest of previous designs for the L2 portion of an
LSSD latch is shown in Fig. 1.  It has unequal set and reset times
due to the difference in ability of NFET 1 to provide as much current
to set the latch as it can when sinking current.

        The new circuit is shown in Fig. 2.  A device of the type of
NFET 1 in the Fig. 1 circuit is split into two pieces, 1A and 1B.
NFET 2 is added.  Inverters I and all other circuit features remain
the same.

        Operation of the new circuit, in the case where the data at
node N1 is a logic LOW, transistor 2 is held off and the latch works
the same as the Fig. 1 latch.  When node N1 is HIGH, transistor 2 is
held on.  When B0 rises, the series combination of transistors 1B and
2 pulls the output of the latching element, node N2, low.  Since the
path through transistors 1B and 2 is sinking current, this path is
much faster than the source follower path through transistor 1A.
Thus, improved latch delay from clo...