Browse Prior Art Database

PVX: A Rule-Based Performance Verification Tool

IP.com Disclosure Number: IPCOM000113800D
Original Publication Date: 1994-Oct-01
Included in the Prior Art Database: 2005-Mar-27
Document File: 4 page(s) / 86K

Publishing Venue

IBM

Related People

Poursepanj, A: AUTHOR [+2]

Abstract

Performance verification is a method of validating the states of CPU logic model during the functional simulation against a set of rules. This is done by checking the values of logic signals, extracted from the simulation database, against a set of equations known as "rules".

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 54% of the total text.

PVX: A Rule-Based Performance Verification Tool

      Performance verification is a method of validating the states
of CPU logic model during the functional simulation against a set of
rules.  This is done by checking the values of logic signals,
extracted from the simulation database, against a set of equations
known as "rules".

      Each rule contains a current cycle condition and a next-cycle
predication.  At the end of each simulation cycle, conditions
conditions specified in the rules are checked.

      If a condition matches, next-cycle condition of the logic is
checked against the specified prediction of the rule.  If they match,
the rule is marked as "Passed", otherwise, the rule is marked as
"Violated".  If the condition of the rule never occurs, it is marked
as "Not fired".

      Rules are written in a C-Like syntax.  Every statements and
expressions are supported by the C compilers except the signal names
that may be either too long or contain characters that may not be
supported by C syntax.

Rules follow the C syntax except the following:
  1.  model name is required in the body of the rule file #model
      name
  2.  signal names are enclosed by two question marks, e.g., ??
      o  negation of a facility name is indicated by placing an
         exclamation point '!' outside the question marks, e.g.,
         !?xxxx?
  3.  Each rule is an integer function with a switch in it.  The
      switch has two cases:
        case CURRENT_CYCLE and case NEXT_CYCLE.

          All the signals under the CURRENT CYCLE are evaluated at
the current unless they are preceded with "next", meaning next
cycle.  In this case parenthesismust enclose the question marks
and "next" is is placed to the left.
  Example 1:
    case CURRENT_CYCLE:
          z = next(?iaa.ida.xsu_instq01(0)?);

          All the signals under the NEXT_CYCLE are evaluated at the
next cycle, unless they are preceded by "p...