Browse Prior Art Database

Dynamic Memory Write Protection for Cache Systems using the Intel 82385-C Cache Controller

IP.com Disclosure Number: IPCOM000113803D
Original Publication Date: 1994-Oct-01
Included in the Prior Art Database: 2005-Mar-27
Document File: 2 page(s) / 46K

Publishing Venue

IBM

Related People

Dixon, RC: AUTHOR

Abstract

This article describes a scheme to prevent writes to the system Read Only Memory (ROM) space, which have been previously cached, from updating the cache.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 100% of the total text.

Dynamic Memory Write Protection for Cache Systems using the Intel
82385-C Cache Controller

      This article describes a scheme to prevent writes to the system
Read Only Memory (ROM) space, which have been previously cached, from
updating the cache.

      Some Personal Computer (PC) software programs write to ROM and
expect ROM data not to change.  Without external circuitry, ROM data
will appear to change as it is read back from the cache.

      The scheme disclosed herein is shown in functional block
diagram in the drawing.  By defining memory write cycles from the
Intel 80386 as Local Bus Accesses (LBA), when addressing ROM memory
space the 82385-C will ignore the 80386 cycle.  It does not cache or
pass the cycle on to the system.

      A solution is to include writes to ROM space in the local bus
access definition.  The local bus accesses are defined by a
Programmable Array Logic (PAL) (Duval T processor card), but other
decode circuitry can be used as well.  The following line added to
the equation for local bus cycles in the decode PAL will provide ROM
memory protection.
  !LBA = CM10.  CWR.! CM31.! CA26.! CA25.! CA24.! CA23.! CA22.!
       CA20. CA19. CA18. CA17. ROMEN

      This is for the case where ROMEN true signals that the ROM data
has been copied to RAM.  Cycles defined as local bus accesses that
write to ROM space are terminated by the local bus wait state
generator.