Browse Prior Art Database

Hardware Assist for DRAM Testing

IP.com Disclosure Number: IPCOM000113805D
Original Publication Date: 1994-Oct-01
Included in the Prior Art Database: 2005-Mar-27
Document File: 2 page(s) / 79K

Publishing Venue

IBM

Related People

Branstad, MW: AUTHOR [+4]

Abstract

Described is a solution for reducing the time it takes to test large amounts of Dynamic RAM. With memory systems growing by rates in orders of magnitude each 3 years, some approach must be used to decrease the time the processor needs to test and initialize this memory. Memory test and initialization generally takes up 90 - 95% of the total hardware test time, and directly adds to the delay of the IPL of the subsystem and system involved. It also adds real-time cost to the manufacturing verification and guardband testing. Decreasing this time makes for both delighted customers and developers.

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Hardware Assist for DRAM Testing

      Described is a solution for reducing the time it takes to test
large amounts of Dynamic RAM.  With memory systems growing by rates
in orders of magnitude each 3 years, some approach must be used to
decrease the time the processor needs to test and initialize this
memory.  Memory test and initialization generally takes up 90 - 95%
of the total hardware test time, and directly adds to the delay of
the IPL of the subsystem and system involved.  It also adds real-time
cost to the manufacturing verification and guardband testing.
Decreasing this time makes for both delighted customers and
developers.

      The solution is to provide hardware assist function that will
streamline DRAM accesses and do repetitive, time-consuming functions
that the processor would normally do in a memory test.  These
functions consist of writing and reading DRAM, doing comparisons on
the read cycles and checking for ECC errors when enabled.  On-chip
memory is provided that stores and compares read data in streaming
mode from the DRAM.  This allows much faster data rates than
traditional processor reads and writes, while still allowing complex
testing.

      An example of the test time decrease can be described with the
following assumptions:  Assuming a 5 MIP processor with slow I/O
cycles, it would take 1.5 micro seconds for a small test loop to run
through once.  The loop code would write 4 bytes, reads back the 4
bytes and compare them.  An 8 Megabyte bank of DRAM (32 bit bus)
would take 3.14 seconds to run through using this test loop
(8,388,608 bytes/4 bytes * 1.5 usec/loo...