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Browse Prior Art Database

Video RAM with Two-Way Interleaving and Power Management Support

IP.com Disclosure Number: IPCOM000113818D
Original Publication Date: 1994-Oct-01
Included in the Prior Art Database: 2005-Mar-27
Document File: 2 page(s) / 35K

Publishing Venue

IBM

Related People

Bland, MM: AUTHOR [+2]

Abstract

Disclosed is a video controller having a 16-bit interface with Video Random Access Memory (VRAM), in which a two-way interleaved VRAM interface and local bus interface are used to improve video performance. This processor also implements power management techniques to reduce power consumption.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 100% of the total text.

Video RAM with Two-Way Interleaving and Power Management Support

      Disclosed is a video controller having a 16-bit interface with
Video Random Access Memory (VRAM), in which a two-way interleaved
VRAM interface and local bus interface are used to improve video
performance.  This processor also implements power management
techniques to reduce power consumption.

      The Figure is a block diagram showing a video controller 10
controlling VRAM 12, which is divided into a first bank 14 and a
second bank 16.  In normal operation, video controller 10 controls
both banks 14 and 16.

      To conserve power, second VRAM bank 16 is disabled by the
activation of the VID_BANK2_DIS bit through software.  For example,
this bit may be set by the BIOS routines or by the operating system
when the power remaining in a battery used to power the computing
system is determined to be low.  In this way a tradeoff is made
between battery life and video performance, such as color and
resolution.  When this bit is active, video controller 10 disables
second bank 16 by driving the XR_VRASn(1) and XR_VC ASn(1) signals to
the VCC level.