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Compile-Time Elimination of Store-Fetch Interlock Delays

IP.com Disclosure Number: IPCOM000113841D
Original Publication Date: 1994-Oct-01
Included in the Prior Art Database: 2005-Mar-27
Document File: 2 page(s) / 54K

Publishing Venue

IBM

Related People

Lipasti, MH: AUTHOR

Abstract

A compile-time technique for eliminating store-fetch interlock delays on Reduced Instruction Set Computer/Cycles (RISC) processors is disclosed. Store-fetch interlocks occur when a store operation to a given memory location is immediately followed by a load from the same location. The interlock is eliminated by reversing the order of the store and load operations and adding an address comparison and conditional select instruction to ensure that the destination register of the load instruction contains the correct value.

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Compile-Time Elimination of Store-Fetch Interlock Delays

      A compile-time technique for eliminating store-fetch interlock
delays on Reduced Instruction Set Computer/Cycles (RISC) processors
is disclosed.  Store-fetch interlocks occur when a store operation to
a given memory location is immediately followed by a load from the
same location.  The interlock is eliminated by reversing the order of
the store and load operations and adding an address comparison and
conditional select instruction to ensure that the destination
register of the load instruction contains the correct value.

      The proposed technique consists of reversing the order of the
load and store instructions, and inserting an explicit compare of the
addresses being used by them, followed by a register-select
instruction that chooses the appropriate value based on the result of
the address comparison.  This explicit comparison eliminates the need
for the implicit address comparison performed by the store-load
combination, and operates as fast or faster than the store-load pair,
whether or not the addresses being referenced are equal.

Figure: Example of Store-Fetch Interlock Elimination
                Original Code            Modified Code
            std   r4,0(r5)        (*)ld    r6,0(r7)
            ld    r6,0(r7)           cmpd  c0,r5,r7
            ...                   (*)std   r4,0(r5)
                              ...