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Complementary Metal Oxide Semiconductor Transistor-to-Transistor Logic Off-Chip Receiver with Integrated Joint Test Action Group Port

IP.com Disclosure Number: IPCOM000113842D
Original Publication Date: 1994-Oct-01
Included in the Prior Art Database: 2005-Mar-27
Document File: 2 page(s) / 80K

Publishing Venue

IBM

Related People

Eisen, LE: AUTHOR [+3]

Abstract

Current design practice for VLSI chips requires that the I/O protocol for these devices be compatible with the requirements set forth by IEEE standards document 1149.1. This is the 'IEEE Standard Test Access Port and Boundary-Scan Architecture' document, also known as the Joint Test Action Group (JTAG) Committee Standard. The purpose of the JTAG standard is to define a methodology which facilitates the testing of VLSI components once they are mounted into a board level assembly. As such, the JTAG guidelines suggest that all Off-Chip Receivers (OCRs) on a chip be followed by a 2:1 multiplexer (MUX) for the injection of test related signals into the normal signal data path.

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This is the abbreviated version, containing approximately 52% of the total text.

Complementary Metal Oxide Semiconductor Transistor-to-Transistor
Logic Off-Chip Receiver with Integrated Joint Test Action Group Port

      Current design practice for VLSI chips requires that the I/O
protocol for these devices be compatible with the requirements set
forth by IEEE standards document 1149.1.  This is the 'IEEE Standard
Test Access Port and Boundary-Scan Architecture' document, also known
as the Joint Test Action Group (JTAG) Committee Standard.  The
purpose of the JTAG standard is to define a methodology which
facilitates the testing of VLSI components once they are mounted into
a board level assembly.  As such, the JTAG guidelines suggest that
all Off-Chip Receivers (OCRs) on a chip be followed by a 2:1
multiplexer (MUX) for the injection of test related signals into the
normal signal data path.  Typically the output drive strength of this
MUX is then increased with the addition of a repower buffer in order
to drive a signal from the periphery of the chip, where the bond pads
are located, to the interior of the chip where the bus interface
logic resides.  These requirements then result in a design for the
OCR as shown in Fig. 1.

      A faster design for a JTAG compliant OCR may be realized
by reducing the number of logic stages in the OCR design shown in
Fig. 1.  This can be accomplished in two ways:
  1.  The line clamp and the 2:1 MUX functions can be combined;
      and
  2.  The repower buffer and the OCR function can be combined.

      A block diagram of this faster JTAG compliant OCR is shown in
Fig. 2.  The intrinsic...