Browse Prior Art Database

Superscalar Processor Rename Bus System

IP.com Disclosure Number: IPCOM000113867D
Original Publication Date: 1994-Oct-01
Included in the Prior Art Database: 2005-Mar-27
Document File: 2 page(s) / 37K

Publishing Venue

IBM

Related People

Burgess, B: AUTHOR [+4]

Abstract

This superscalar microprocessor register renaming system uses rename forwarding buses with integral rename buffer latches. This approach uses minimum area and associated control logic.

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Superscalar Processor Rename Bus System

      This superscalar microprocessor register renaming system uses
rename forwarding buses with integral rename buffer latches.   This
approach uses minimum area and associated control logic.

      In the following System Diagram, the rename buses are shown
connected to the output and input of several function units.  The
rename buffers are built into the buses as holding latches and
require no control logic.  The latches are implemented as
back-to-back inverters with the latch output to the bus being weakly
driven as shown in the Detail Diagram.  Thus, when new data is
written on the bus by the bus drivers in the execution unit, the
previous stale data is overwritten.  The results are driven onto the
rename bus during a dedicated portion of the clock cycle and
automatically stored by the rename holding latche.

      The advantages of this system are 1) minimum silicon area,
2) fast forwarding of execution unit results to subsequent units
including to itself, and 3) no control logic for the holding latches.