Browse Prior Art Database

Diagnostic Cache Scratchpad Mode for Testing Personal Computers

IP.com Disclosure Number: IPCOM000113870D
Original Publication Date: 1994-Oct-01
Included in the Prior Art Database: 2005-Mar-27
Document File: 2 page(s) / 68K

Publishing Venue

IBM

Related People

Aldereguia, A: AUTHOR [+7]

Abstract

Described is a software implementation to provide a diagnostic cache scratchpad mode for isolation testing of Personal Computers (PCs). A read/write memory, in close proximity to the Central Processing Unit (CPU), is used to provide cache scratchpad testing so as to meet Reliability, Availability and Serviceability (RAS) requirements and to improve the isolation of malfunctions.

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Diagnostic Cache Scratchpad Mode for Testing Personal Computers

      Described is a software implementation to provide a diagnostic
cache scratchpad mode for isolation testing of Personal Computers
(PCs).  A read/write memory, in close proximity to the Central
Processing Unit (CPU), is used to provide cache scratchpad testing so
as to meet Reliability, Availability and Serviceability (RAS)
requirements and to improve the isolation of malfunctions.

      In prior art, the testing of computers required special coding
in the startup of RAS routines to compensate for the lack of
read/write stack memories.  For example, the special coding involved
making a call to a subroutine and the stack pointer had to be changed
to point to a table in Read Only Memory (ROM) which had the
appropriate return address.  Also, the cache could only be tested
after the memory, external to the processor, was tested.  An
important feature of the RAS requirements is to test functions
nearest the processor and to migrate the tests to hardware and
function further and further away from the processor.

      Memory elements that were physically located on a local bus,
other than those near the CPU required that every function on the
local bus had to be tested prior to the memory unit testing in order
to meet RAS requirements.  The concept described herein provides a
means that allows an existing memory source, close to the CPU, to
behave similarly to a dynamic RAM device in the PC system.

      Typically, standard cache memory devices of the store-through
or store-in variety are loaded by transferring a cache line in
multiple words from another memory into the cache.  In some PC
operations, the memory signals come from a bus tha...