Browse Prior Art Database

Synchronization of Firmly Coupled Multiple Processors

IP.com Disclosure Number: IPCOM000113880D
Original Publication Date: 1994-Oct-01
Included in the Prior Art Database: 2005-Mar-27
Document File: 4 page(s) / 77K

Publishing Venue

IBM

Related People

Geer, CP: AUTHOR [+6]

Abstract

Disclosed is an artificial means for testing purposes by which the processors in a tightly- and firmly-coupled Multiple Processor (MP) system can be synchronized to begin processing at some test case defined starting point.

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This is the abbreviated version, containing approximately 52% of the total text.

Synchronization of Firmly Coupled Multiple Processors

      Disclosed is an artificial means for testing purposes by which
the processors in a tightly- and firmly-coupled Multiple Processor
(MP) system can be synchronized to begin processing at some test case
defined starting point.

      The MP Sync function (MPSYNC) is supported by latches and logic
in the processor chip.  The MPSYNC register is a register which can
be read or written by the processor.  MPSYNC register contains three
bits visible to software.  They are MPSYNC[IN], MPSYNC[OUT], and
MPSYNC[BREAK], as shown in Fig. 1.
  Term            Definition
  0-28            reserved
  29              MPSYNC[OUT]  turns on the MPSYNCO and MPSYNCX
                  processor outputs when 1.
  30              MPSYNC[IN]  is used to detect the state of the
                  MPSYNXI input.
  31              MPSYNC[BREAK]  breaks the propagation chain of
                  MPSYNXI.

      There are two module outputs driven from the first processor in
each module.  The one called MPSYNCO is the output which is fed to
the second processor in the first module and to the first processor
in the second module.  This signal should only take one cycle to
propagate.  There is a second output MPSYNCX which is sent to the
first processor in the next node and to a connector on the board.  In
a system with more than one processor board, the board connector is
used to propagate the signal via an optional cable to the next
processor board.  This signal is treated as an a...