Browse Prior Art Database

Automatic Process for Fixing Fastpath Problems in Control Logic

IP.com Disclosure Number: IPCOM000113913D
Original Publication Date: 1994-Oct-01
Included in the Prior Art Database: 2005-Mar-27
Document File: 2 page(s) / 47K

Publishing Venue

IBM

Related People

Golla, RT: AUTHOR

Abstract

Designs must be free of fast paths in order to work properly. The class of fast paths examined here involves the problem of propagating through latch boundaries unintentionally. This class of fast paths can arise whenever a latch output directly feeds another latch input with little or no intervening logic and each latch is sourced by different clock generators. If sufficient skew exists between the two clock generators, and the delay between the latches is small enough, it is possible to have a path that propagates through the downstream latch and into another latch within a single machine cycle. Historically, designers have been forced to identify and fix these fastpath problems by hand.

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Automatic Process for Fixing Fastpath Problems in Control Logic

      Designs must be free of fast paths in order to work properly.
The class of fast paths examined here involves the problem of
propagating through latch boundaries unintentionally.  This class of
fast paths can arise whenever a latch output directly feeds another
latch input with little or no intervening logic and each latch is
sourced by different clock generators.  If sufficient skew exists
between the two clock generators, and the delay between the latches
is small enough, it is possible to have a path that propagates
through the downstream latch and into another latch within a single
machine cycle.  Historically, designers have been forced to identify
and fix these fastpath problems by hand.

      The majority of potential fastpaths encountered in practice
involve latch to latch paths with no intervening logic and each latch
is sourced by a different clock generator.  A process has been
developed to automatically detect and fix these potential fastpath
problems.  The process involves two steps: 1) identify the potential
fastpath cases 2) fix the fastpaths themselves by inserting buffers.
A 'C' program called FASTPATH written in DADB has been developed to
identify the fastpaths.  It processes an entire chip and finds
latches that meet the fastpath criteria outlined above.  A file is
written to identify these latches.  A second program called FIXRLMFP
actually inserts the buffers between t...