Browse Prior Art Database

Monitoring Method for Micro Channel Personal Computers

IP.com Disclosure Number: IPCOM000113924D
Original Publication Date: 1994-Oct-01
Included in the Prior Art Database: 2005-Mar-27
Document File: 4 page(s) / 105K

Publishing Venue

IBM

Related People

Huynh, DQ: AUTHOR [+2]

Abstract

Described is an architectural implementation to provide a means of ensuring the integrity of cacheable memory data shared between a processor's cache and the Micro Channel* (MC). The implementation is designed to maintain data coherency in a PC system by monitoring the MC bus master cycles and to generate a snoop cycle to the processor when cacheable memory is accessed.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 52% of the total text.

Monitoring Method for Micro Channel Personal Computers

      Described is an architectural implementation to provide a means
of ensuring the integrity of cacheable memory data  shared between a
processor's cache and the Micro Channel* (MC).  The implementation is
designed to maintain data coherency in a PC system by monitoring the
MC bus master cycles and to generate a snoop cycle to the processor
when cacheable memory is accessed.

      Typically, PC processors, which utilize an internally stored-in
cache, require that the integrity of the data shared between the
processor and other bus masters be protected.  When a bus master
accesses a system memory location, which has been modified by the
processor in the stored-in cache, the modified data must be written
back to the system memory before the bus master is allowed to access
that data.

      The concept described herein is designed to ensure the
integrity of the cacheable memory data shared between the processor's
stored- in cache and the MC bus masters.  The MC bus master cycles
are continuously monitored such that when a bus master requests
access to the cacheable system memory, during either a read or write
cycle, a snoop cycle will be initiated to the processor.  If the
snoop cycle hits a modified cache line, the bus master cycle will be
suspended and the processor will immediately schedule a write back
cycle to update the system memory.  Only when the memory location has
been updated will the MC bus master cycle be allowed to resume
operation.

      The bus master signal is used to detect whether an MC bus
master owns the bus or not.  If true, the monitoring logic will
inspect MCA_S0#, MCA_S1#, MCA_M/IO# for a memory cycle.  Once a
memory cycle has been detected, the bus controller will decode the
address t...