Browse Prior Art Database

Condition Code Generation for Three-Leg Adder with Dependent Adder Instructions

IP.com Disclosure Number: IPCOM000113943D
Original Publication Date: 1994-Oct-01
Included in the Prior Art Database: 2005-Mar-27
Document File: 4 page(s) / 97K

Publishing Venue

IBM

Related People

Ray, DS: AUTHOR [+2]

Abstract

In the RIOS-2 Fixed Point dual execution unit processor design the second execution unit contains a three operand adder that allows the Fixed Point chip to execute two dependent adder operations in one cycle. In addition to being required to generate a correct result in the execute cycle, the execute cycle logic is also required to generate the condition codes for the current instruction. The requirement to generate the condition codes in the execute cycle is a performance statement that allows the RIOS-2 Fixed Point and the Instruction Cache to achieve a 1 cycle compare branch penalty, the compares with a 3 cycle compare branch penalty in the RIOS-1 design. A diagram of the adders found in the execution units is shown in Fig. 6.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 52% of the total text.

Condition Code Generation for Three-Leg Adder with Dependent Adder
Instructions

      In the RIOS-2 Fixed Point dual execution unit processor design
the second execution unit contains a three operand adder that allows
the Fixed Point chip to execute two dependent adder operations in one
cycle.  In addition to being required to generate a correct result in
the execute cycle, the execute cycle logic is also required to
generate the condition codes for the current instruction.  The
requirement to generate the condition codes in the execute cycle is a
performance statement that allows the RIOS-2 Fixed Point and the
Instruction Cache to achieve a 1 cycle compare branch penalty, the
compares with a 3 cycle compare branch penalty in the RIOS-1 design.
A diagram of the adders found in the execution units is shown in Fig.
6.

      The problem solved by this invention is how to generate the
four condition code bits correctly when executing two inherently
sequential instructions such as
 A R1,R2,R3
 A R4,R1,R5
in one cycle.  Note how the result of the first instruction R1 is the
RA operand of the second instruction.  In a traditional computer
these two instruction must be executed sequentially in order to
produce the correct result.  In the RIOS-2 Fixed Point chip the use
of the three leg adder allows us to execute these two instructions in
parallel.

      For RIOS-2 there are several instructions pairs that benefit
from the 3 leg adder.  The instruction fall into the following
groups:
 1.  Add followed by Add
 2.  Add followed by Subtract/Compare
 3.  Subtract/Compare followed by Add
 4.  Subtract/Compare followed by Subtract

      Each of these four groups have two bypass cases, these bypasses
can best be illustrated by the example shown in Fig. 1.

      The first case is called the `ra' bypass.  This is because in
the second add ra is replaced with the result of the first add.  The
second case is called the `rb' bypass.  This is because in the second
ad...