Browse Prior Art Database

Enhanced Refresh Mechanism for Higher Performance in Memory Subsystems

IP.com Disclosure Number: IPCOM000113945D
Original Publication Date: 1994-Oct-01
Included in the Prior Art Database: 2005-Mar-27
Document File: 4 page(s) / 109K

Publishing Venue

IBM

Related People

Lang, DJ: AUTHOR [+3]

Abstract

An improved method for performing refreshes in systems with volatile memories such as Dynamic Random Access Memories (DRAM) and Synchronous Dynamic Random Access Memories (SDRAM) is disclosed. The scheme uses a priority mechanism to decide the winner in a contention situation. The scheme is dynamic to schedule refreshes for idle banks of memory while a different bank may be getting accessed.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 52% of the total text.

Enhanced Refresh Mechanism for Higher Performance in Memory Subsystems

      An improved method for performing refreshes in systems with
volatile memories such as Dynamic Random Access Memories (DRAM) and
Synchronous Dynamic Random Access Memories (SDRAM) is disclosed.  The
scheme uses a priority mechanism to decide the winner in a contention
situation.  The scheme is dynamic to schedule refreshes for idle
banks of memory while a different bank may be getting accessed.

      Problem - One of the major performance degraders associated
with memory subsystems that utilize DRAMs or SDRAMs is that they
require a refresh operation to be scheduled to a memory location at
least once within a refresh period.  A typical refresh period is 15.6
micro-seconds.  This requirement to perform a refresh causes a
functional request to the memory to be delayed thereby causing "wait
states"  in the processor.  The invention outlined in this document
solves the refresh performance penalty.

      Solution - This invention advances the state of the art by
solving the refresh performance problems by dividing the refresh
period for the memory into two main zones.  They are "low priority"
and "high priority." In addition to having two zones, the design
allows the transition from low to high priority to be programmable so
as to optimize the scheme for memory performance based on workload
types.

      During the "low priority"  time slot, a refresh request to a
memory location is honored only if the memory address is idle and
there are no functional requests to that particular memory address.
If a low priority refresh is completed, the refresh causes no
performance degradation in the system.  During a "high priority"
time slot, the refresh is honored regardless of system work-load.
This is necessary in orde...