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Configuration and Control Interface for a Fibre Channel Protocol Chip

IP.com Disclosure Number: IPCOM000113949D
Original Publication Date: 1994-Oct-01
Included in the Prior Art Database: 2005-Mar-27
Document File: 4 page(s) / 116K

Publishing Venue

IBM

Related People

Nordstrom, GM: AUTHOR

Abstract

A control and status interface is described suitable for microprocessor control of a hardware implementation of the ANSI Fibre Channel FC-1 and FC-2 protocols.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 52% of the total text.

Configuration and Control Interface for a Fibre Channel Protocol Chip

      A control and status interface is described suitable for
microprocessor control of a hardware implementation of the ANSI Fibre
Channel FC-1 and FC-2 protocols.

      The ANSI Fibre Channel FC-1 and FC-2 protocols suggest an
implementation composed of both hardware (ASIC) and microprocessor
elements.  Typically, microprocessor elements perform the
transformation of I/O device or network communications protocols to
or from Fibre Channel FC-1 and FC-2 link transport protocols, as well
as the association between the Fibre Channel encapsulation of data on
a Fibre Channel link and its organization and location within the
application node that contains a Fibre Channel N_Port (e.g., a
computer's main storage).  Hardware, in turn, typically implements
the high-speed transformation of data and control information to the
atomic units of the FC-2 and FC-1 protocols, such as Sequences,
Frames, Primitive Sequences, and Ordered Sets.

      Crucial to the efficiency of such an implementation is the
interface between the microprocessor and the hardware elements.  This
interface is characterized by interactions related primarily to link
initialization and recovery events, and Fibre Channel Sequence
boundaries.  In general, the elements of this interface include:
  o  indications to the microprocessor of the protocol chip's FC-1
and
     FC-2 capabilities;
  o  controls that allow the microprocessor to configure or modify
the
     FC-1 and FC-2 capabilities and operations of the protocol chip;
and
  o  controls that allow the microprocessor to establish protocol
chip
     operating parameters required for Fibre Channel communications
     tailored to a particular operating environment (e.g., a computer
     vs. a DASD Controller) or to particular I/O device or
     communications protocols.

Specific definitions of these interface elements are:
  a Hardware Configuration Register describing the protocol chip's
  physical media configuration and operational capabilities.

This register contains:
  o  Concurrent Sequences: the total number of concurrent
     sequences, combined over all protocol classes, that the
     protocol chip can support.
  o  FH-PH Version: the standard level of FC-PH implemented
     by the FC2P chip
  o  Transmitter Parameters: identifies the characteristics -- such
     as baud rate, optical medium, distance capability, etc -- of
     the FC-0 component attached to the protocol hardware and allows
     for interchangeability of FC-0 component types.
  o  Maximum Receive Frame Size: records the maximum frame
     buffer provided by the protocol hardware or N_Port adapter.

Link Status Register conveys the dynamic state of the Fibre Channel
link to the microprocessor and includes status such as:
  o  FC-1 Connection Status: Not Connected, Connect Pending
     (connect_try), e...