Browse Prior Art Database

Bus Deskewing Method using a Self-Adjusting Variable Delay Element

IP.com Disclosure Number: IPCOM000113950D
Original Publication Date: 1994-Oct-01
Included in the Prior Art Database: 2005-Mar-27
Document File: 2 page(s) / 100K

Publishing Venue

IBM

Related People

Georgiou, GJ: AUTHOR [+2]

Abstract

Disclosed is a method to synchronize a group of signals that are launched simultaneously from a sender over multiple bus lines but arrive at a receiving end skewed in time due to the inherent delay mismatches along the physical transmission path. The synchronization is achieved at the receiving end by adjusting the propagation delay of each signal in a parallel fashion. The disclosed method includes means of estimating the arrival time of each skewed signal and compensating the arrival time differences among the input signals by providing a self-adjusting variable delay chain along the signal paths.

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Bus Deskewing Method using a Self-Adjusting Variable Delay Element

      Disclosed is a method to synchronize a group of signals that
are launched simultaneously from a sender over multiple bus lines but
arrive at a receiving end skewed in time due to the inherent delay
mismatches along the physical transmission path.  The synchronization
is achieved at the receiving end by adjusting the propagation delay
of each signal in a parallel fashion.  The disclosed method includes
means of estimating the arrival time of each skewed signal and
compensating the arrival time differences among the input signals by
providing a self-adjusting variable delay chain along the signal
paths.

      The disclosed method addresses a fundamental problem
encountered in the attempt to achieve higher bandwidth on parallel
buses.  Increasing the width of the bus beyond a certain upper bound
is limited due to the performance limitations of card-level packaging
and hardware cost.  Using shorter bus cycle times requires either
very tight control of timing skews on the parallel signals with
respect to the bus clock or employing a bus deskewing mechanism to
synchronize the bus signals at the receiving end.  The tight control
of the bus timing skew within a fraction of a bus cycle can be very
difficult to achieve at reasonable hardware costs.

      The disclosed deskewing method for a group of 'n' input signals
comprises 'n' identical deskewing modules with an associated control
logic, as shown in the Figure.  Each deskewing module consists of a
chain of variable delay elements connected serially.  Each variable
delay element is made of a master/slave data sampling flip-flop
(i.e., delay control flip-flop), a delay line, and a 2-to-1
multiplexer.  The variable delay element provides two different
signal paths with different signal propagation delays.  When the
selection signal (i.e., SELECT, the output from the delay control
flip-flop) is TRUE, the delay element is selected.  The control logic
provides the necessary timing signals to initialize the delay control
flip-flops (PRESET) and load appropriate data into the delay control
flip-flops (SET_DELAY).  Once appropriate data is loaded into the
delay control flip-flops, the total propagation delay of the variable
delay chain along each input signal is set in su...