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Automatic Assertion Generation for Logic Synthesis

IP.com Disclosure Number: IPCOM000113958D
Original Publication Date: 1994-Oct-01
Included in the Prior Art Database: 2005-Mar-27
Document File: 2 page(s) / 77K

Publishing Venue

IBM

Related People

Golla, RT: AUTHOR [+2]

Abstract

Logic synthesis maps high level descriptions of logic into actual gates. These high level descriptions of a given piece of logic can be considered to be random logic macros (RLMs). RLMs often describe the control logic of a microprocessor. In order to achieve the best logic synthesis for RLMs, the proper assertions for the RLM must be generated. These assertions consist of primary input arrival times, expected primary output departure times and the capacitance on the primary outputs. These files can be generated by hand, but doing so is time-consuming and error-prone. Moreover, maintaining these files can prove impossible during the many changes that invariably occur during the development of a microprocessor.

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Automatic Assertion Generation for Logic Synthesis

      Logic synthesis maps high level descriptions of logic into
actual gates.  These high level descriptions of a given piece of
logic can be considered to be random logic macros (RLMs).  RLMs often
describe the control logic of a microprocessor.  In order to achieve
the best logic synthesis for RLMs, the proper assertions for the RLM
must be generated.  These assertions consist of primary input arrival
times, expected primary output departure times and the capacitance on
the primary outputs.  These files can be generated by hand, but doing
so is time-consuming and error-prone.  Moreover, maintaining these
files can prove impossible during the many changes that invariably
occur during the development of a microprocessor.

      A program called ASSERT has been developed to automatically
generate the assertions for synthesis for all of the RLMs within a
given microprocessor design.  ASSERT is a 'C' program written within
the dadb application programming interface.  It runs in conjuction
with a static timer called STEP in order to automatically generate
the proper assertions for the RLMs.  STEP provides incore access to
arrival times and slack information.  ASSERT is very fast since all
of the information it needs is incore within the dadb database.  The
number of calculations required by ASSERT is equal to the total
number of RLM inputs and outputs.  The calling sequence to ASSERT is:
 call assert GPROTO FPROTO GCLKS IDSP_CYCLE CHIP_CYCLE.

      GPROTO is the global proto for the microprocessor at hand.  It
includes all of the global interconnect for the chip.  The internal
wiring of the RLMs does not exist at the global level.  FPROTO is the
flat proto for the chip.  All rlms have been expanded to their gate
level representations at this level.  GCLK is the global clock for
the chip (it is assumed that there is one global clock for the chip).
IDSP_CYC...