Browse Prior Art Database

Combined Status and Message-In Function for Small Computer System Interface

IP.com Disclosure Number: IPCOM000113962D
Original Publication Date: 1994-Oct-01
Included in the Prior Art Database: 2005-Mar-27
Document File: 2 page(s) / 72K

Publishing Venue

IBM

Related People

Cooke, DC: AUTHOR [+5]

Abstract

Disclosed is the combination, within a SCSI 2 (Small Computer System Interface, version 2) Micro Channel* adapter, of the Status and Message-In Protocols into a single SMI (Status and Message In) state machine producing a single interrupt. Without this combination, the Status and Message In protocols require four or more interrupts.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 52% of the total text.

Combined Status and Message-In Function for Small Computer System
Interface

      Disclosed is the combination, within a SCSI 2 (Small Computer
System Interface, version 2) Micro Channel* adapter, of the Status
and Message-In Protocols into a single SMI (Status and Message In)
state machine producing a single interrupt.  Without this
combination, the Status and Message In protocols require four or more
interrupts.

      When the SMI state machine is enabled, it waits in an idle
state for a valid Status phase.  If the SCSI controller chip has no
pending interrupts, the state machine latches the status into the
status portion of the SMI Data Register (3Eh), asserting ACK
(Acknowledge) after the target asserts REQ (Request).  If an
interrupt from another state machine is pending, the SMI state
machine waits for the other interrupt to be serviced before asserting
ACK.  The SMI logic continues to drive ACK until the target releases
REQ.

      Next, the SMI state machine expects the phase to change to
Message In before REQ is asserted again.  If REQ is active and the
phase is not Message In, the SMI logic sets the Message Phase
Mismatch Bit in the SMI Control Register (3Ch) and posts a interrupt.
The SMI state machine also checks to see if the Status data was
"GOOD" (00h) or not.  If REQ is active and the previous Status Byte
was anything but "GOOD," the SMI sets the Status Error Bit in the SMI
Control Register (3Ch), the Message In Byte is latched in the message
portion of the SMI Data Register (3Eh), and an interrupt is posted.
If the phase is correct, the Status Byte is "GOOD" and REQ is active,
the SMI state machine latches the Message In data and checks for
COMMAND COMPLETE (00h).  At this point, if the Message In Byte is
anything but COMMAND COMPLETE, the SMI state machine sets Message
Error Bit in the SMI Control Register (3Ch), posting an interrupt.
If the Message In byte is COMMAND COMPLETE, the SMI state machine
asserts ACK.

      The SMI state machine then continues to assert ACK until the
target releases the REQ for the Message In byte.  When REQ becomes
inactive the SMI no longer asserts ACK, setting the SMI Complete bit
in the SMI Control Register (3Ch) and posting an interrupt to
indicate the successful completion.

      Thus, The SMI state machine efficiently combines several
functions of the SCSI p...