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Divide-by-2 Clock Circuit

IP.com Disclosure Number: IPCOM000113967D
Original Publication Date: 1994-Oct-01
Included in the Prior Art Database: 2005-Mar-27
Document File: 4 page(s) / 121K

Publishing Venue

IBM

Related People

Bilings, RV: AUTHOR [+5]

Abstract

As microprocessors' (and all integrated circuits') frequencies continue to increase, clock generation and distribution become more important. Issues becoming more important include the duty cycle, the amount of power and the size of the silicon consumed by the clock generation and distribution. The Phase Locked Loop (PLL) is probably the most common solution to high frequency clock generation. However, its use is certainly not without cost; the area and power are not insignificant. An additional concern in some design environments is the difficulty in testing the PLLs.

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Divide-by-2 Clock Circuit

      As microprocessors' (and all integrated circuits') frequencies
continue to increase, clock generation and distribution become more
important.  Issues becoming more important include the duty cycle,
the amount of power and the size of the silicon consumed by the clock
generation and distribution.  The Phase Locked Loop (PLL)  is
probably the most common solution to high frequency clock generation.
However, its use is certainly not without cost; the area and power
are not insignificant.  An additional concern in some design
environments is the difficulty in testing the PLLs.

      The alternative utilized on the 601 is a small (2 latches, 8
inverters and 1 2-input NAND gate) divide by 2 circuit.  As the name
implies, the circuit receives a clock input and divides the frequency
of it by 2 before distributing the clock to the rest of the chip.
The advantage of doing this is the less stringent requirements placed
on the input clock; it could have a duty cycle of 30/70 and the
output of the divide by 2 circuit will have a duty cycle of roughly
51/49 (more on this with the design details).  In addition to the 2X
clock input, the divide-by-2 also receives a clock at the desired
frequency to synchronize the clock with the rest of the system (it
would be unacceptable to have the chips' clock 180 degrees out of
phase with the rest of the system).

      Fig. 2 601 system clocking example.

Design Details - Fig. 1 is a block diagram of the divide-by-2 circuit
in the 601.  As mentioned above, its inputs are the 2X_PROC_CLOCK and
the CLOCK_PHASE signals (clocks at 2 times the desired frequency and
the desired frequency, respectively).  The latches are clocked with
the 2X signal and the data input is the CLOCK_PHASE.  Putting
CLOCK_PHASE on the input and the inverter between the L1 latch and
the L2 latch makes the output of the divide-by-2 a sharper (better
rise and fall times and a better duty cycle) version of the
CLOCK_PHASE signal.  The inverters and NAND gate which the 2X signal
passes through is known as a `clock chopper' (1).  The clock chopper
is included to ensure the CLOCK_PHASE signal is stable before the L1
latches it in.  Precise delay circuits, an alternative way to ensure
that CLOCK_PHASE is stable before it is latched, utilizes a
prohibitive amount of area.

      To fully ap...