Browse Prior Art Database

PowerPC 601/604 Multiprocessor Random Verification Methodology

IP.com Disclosure Number: IPCOM000113973D
Original Publication Date: 1994-Oct-01
Included in the Prior Art Database: 2005-Mar-27
Document File: 6 page(s) / 239K

Publishing Venue

IBM

Related People

Glenn, SC: AUTHOR

Abstract

Disclosed is a functional design verification methodology for Multi-Processor (MP) simulation models of PowerPC* microprocessors.

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This is the abbreviated version, containing approximately 25% of the total text.

PowerPC 601/604 Multiprocessor Random Verification Methodology

      Disclosed is a functional design verification methodology for
Multi-Processor (MP) simulation models of PowerPC* microprocessors.

      One of the major goals in the design of the PowerPC 601* and
PowerPC 604* microprocessors and the PowerPC Architecture* is support
for multiprocessing (1).  The amount and complexity of logic required
to support MP presents a verification concern to the design and
verification engineers of the microprocessors.  In uniprocessor
verification methodologies, the results of any given sequence of
instructions executed by a single microprocessor are deterministic.
That is, results for the microprocessor's own resources and system
resources can be predicted for any sequence of instructions generated
by a simple testcase generator.  However, in a multiprocessor
environment using shared resources, results of the execution of a
sequence of instructions and system resources are non-deterministic.
Thus, the uniprocessor methodology cannot be reused.  Furthermore,
there exists a vast number of MP scenerios that require multiple
processors performing accesses at the same time as well as a large
number of processor (cache) states possible in a 3-way MP system.
This invention solves the multiprocessor verification problems by
introducing a methodology that is capable of generating, through
assembly testcases, the small cross-section of MP scenerios and a
large number of states as required.

      The functional design verification of an MP microprocessor must
include the verification of many aspects of a multiprocessor model.
These include Memory Management, the serialization of memory reads
and writes should occur as if they were executed on a uniprocessor
system, Cache Coherency, the verification of coherency between
multiple caches and main memory in a write-through and write-back
cache policy model, and finally, Locking and Synchronization, locking
and synchronization algorithms for accessing shared data or code.

      The Multiprocessor Random Verification Methodology (MRVM)
solves the problems with non-determinism and coverage of a large
number of MP states with random MP assembly testcases.  This
methodology may be used for all PowerPC microprocessor
implementations and is extremely flexible to address a wide variety
of MP scenerios.  It requires an implementation-specific
pseudo-Random Testcase Program Generator (RTPG) (2), an MP system
simulation model of the microprocessor under test, Random Testcase
Executor (RTX), and the Texsim system simulator.  A description of
these items can be found in documentation as listed in the reference.

      This MRVM assumes a successful completion of a uniprocessor
verification methodology.  The uniprocessor methodology should have
completely exercised the entire microprocessor complex with
deterministic testcases.  In any random verification methodology, the
approach is to use bia...