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Level Sensitive Scan Design Scan Chain Latch Retention Test for VLSI Automatic Test Equipment

IP.com Disclosure Number: IPCOM000113978D
Original Publication Date: 1994-Oct-01
Included in the Prior Art Database: 2005-Mar-27
Document File: 2 page(s) / 51K

Publishing Venue

IBM

Related People

Hassing, KE: AUTHOR [+2]

Abstract

Disclosed is a method to detect L1-L2 LSSD scan latch defects. This test method concentrates on the value holding ability of scan latches. Latch holding defects are typically undetected with high speed digital testing methods.

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Level Sensitive Scan Design Scan Chain Latch Retention Test for VLSI
Automatic Test Equipment

      Disclosed is a method to detect L1-L2 LSSD scan latch defects.
This test method concentrates on the value holding ability of scan
latches.  Latch holding defects are typically undetected with high
speed digital testing methods.

      Create a latch-hold retention test for a VLSI tester by
generating a set of stimulus patterns based on a scan latch test.  In
the scan latch test the pairs of L1-L2 latches are loaded with
alternating pairs of '1's and '0's.  The L1-L2 double latch
configuration is shown in Fig. 1.  A scan chain typically would
consist of thousands of L1-L2 pairs connected in a chain.

      The pairs of L1-L2 latches propagate their values propagate
during the scan latch test for each A-clock pulse and B-clock pulse
as shown in Fig. 2.
       latch    N     N+1    N+2    N+3
     Clock    L1-L2  L1-L2  L1-L2  L1-L2
    (initial) 1  1   1  1   0  0   0  0
      A       0  1   1  1   1  0   0  0
      B       0  0   1  1   1  1   0  0
      A       0  0   0  1   1  1   1  0
      B       0  0   0  0   1  1   1  1
      A       1  0   0  0   0  1   1  1
      B       1  1   0  0   0  0   1  1
      A       1  1   1  0   0  0   0  1
      B       1  1 ...