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Non-Clock Slivering High-Speed Word Recognizer for a Serial Shift Register

IP.com Disclosure Number: IPCOM000113980D
Original Publication Date: 1994-Oct-01
Included in the Prior Art Database: 2005-Mar-27
Document File: 4 page(s) / 98K

Publishing Venue

IBM

Related People

Freitag, LW: AUTHOR [+4]

Abstract

A non-clock slivering word recognizer for a serial shift register is disclosed. When a byte sync word is detected, the output clocks are not immediately reset, which prevents slivering of the output clocks.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 52% of the total text.

Non-Clock Slivering High-Speed Word Recognizer for a Serial Shift
Register

      A non-clock slivering word recognizer for a serial shift
register is disclosed.  When a byte sync word is detected, the output
clocks are not immediately reset, which prevents slivering of the
output clocks.

      When data words (bytes) are encoded and Time-Division
Multiplexed (TDM) into a serial stream of data, a unique word (byte
sync word) that is assured not to be a conjunction of two words must
be provided.  This permits the circuit that receives the data to
demultiplex whole words that are not fragmented (conjunctions of two
transmitted words).  When the byte sync word is detected, a state
machine is reset.  This can cause the clocks generated by this state
machine to be shrunk in period (slivered).  A circuit is proposed to
prevent this slivering.

      The block diagram for the demultiplexing logic is shown in Fig.
1.  A Phase Locked Loop (PLL) realizes the phase orientation between
the clock and serial data shown in the figure.  The clock and data
are fed to a rising-edge triggered 12 bit shift register.  The shift
register consists of 12 differential positive transition D type
master slave flip-flops.

      After loading the byte sync word into the first 10 bits of the
shift register, the byte sync detector sends a pulse to the decade
counter on the next rising edge of the clock.  The data in the shift
register also shifts one bit on this clock edge.  The decade counter,
which is a Johnson counter with state correction, is set on the next
rising edge of the clock.  Again, the data is shifted one bit in the
shift register.  Fig. 2.   Anti-Clock Slivering Circuit.

      Two outputs from the decade counter are NORed together to
construct the load signal to the first 10-bit polarity hold register.
The same two outputs are inverted and then NORed together to
construct the load signal to the second 10-bit polarity hold
register.  When t...