Browse Prior Art Database

Physical Address Registers for a Fibre Channel Protocol Chip

IP.com Disclosure Number: IPCOM000113992D
Original Publication Date: 1994-Oct-01
Included in the Prior Art Database: 2005-Mar-27
Document File: 2 page(s) / 89K

Publishing Venue

IBM

Related People

Nordstrom, GM: AUTHOR

Abstract

A facility is described that provides an efficient hardware method of link physical address recognition for a multiplicity of link physical addresses that identify -- or "alias" -- a singular network physical interface. Application of this facility is particularly related to the proposed ANSI standard Fibre Channel, and similar frame-based communications networks and I/O channels.

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This is the abbreviated version, containing approximately 52% of the total text.

Physical Address Registers for a Fibre Channel Protocol Chip

      A facility is described that provides an efficient hardware
method of link physical address recognition for a multiplicity of
link physical addresses that identify -- or "alias" -- a singular
network physical interface.  Application of this facility is
particularly related to the proposed ANSI standard Fibre Channel, and
similar frame-based communications networks and I/O channels.

      Some I/O channel and fiber optic communications protocols
organize data into "packets," or "frames", for the purposes of
transmission from one node on the medium to another.  These protocols
commonly include the identifier of the destination node -- usually
its "physical address" on the medium -- as part of the leading
information contained in a frame or packet.  Additionally, a single
physical node on a communications medium may be known to other nodes
on that medium by multiple different addresses, and therefore must be
capable of recognizing any of these different identifiers within a
frame transmitted on the medium.

A node that has multiple physical addresses must be capable both of:
 1.  selecting a specific address value when originating frame or
    packet transmissions, and
 2.  recognizing and responding to any of its addresses as the
    recipient of frames or packets.

      To accomplish these address recognition and origination
functions, the hardware that interfaces the node to the physical
medium may contain an array of "alias registers", indexed from 0 to
"n", that are comprised each of:
 1.  an address field to record the medium physical addresses that
the
    node uses to send or receive frames;
 2.  a compare mask field that may be conditionally used during frame
    reception to extend the range of addresses recognizable with
    particular register's recorded address value; and
 3.  enable and mask control bits.

          The "enable" bit controls whether or not that register, and
    its address field content, may be used for frame transmission or
    reception.  When logically "on", the node interface hardware may
    use that alias register for frame transmission or reception.  A
    node may use the enable control to dyna...