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32 Bit VXI Register Based Interface using Field Programmable Gate Arrays

IP.com Disclosure Number: IPCOM000113997D
Original Publication Date: 1994-Oct-01
Included in the Prior Art Database: 2005-Mar-27
Document File: 2 page(s) / 99K

Publishing Venue

IBM

Related People

Catino, A: AUTHOR [+2]

Abstract

32 Bit VXI Register Based Interface using Field Programmable Gate Arrays implemented as a C-size VXI card, with area available for custom user logic, supporting the following VXI features: Register Based, Dynamic Configuration, A16/A32 Addressing Mode, D08, D16, and D32 Data Paths, VME Block Mode Transfers, Configuration Registers, VME Interrupts, and TTL Triggers.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 52% of the total text.

32 Bit VXI Register Based Interface using Field Programmable Gate
Arrays

      32 Bit VXI Register Based Interface using Field Programmable
Gate Arrays implemented as a C-size VXI card, with area available for
custom user logic, supporting the following VXI features:  Register
Based, Dynamic Configuration, A16/A32 Addressing Mode, D08, D16, and
D32 Data Paths, VME Block Mode Transfers, Configuration Registers,
VME Interrupts, and TTL Triggers.

      This article describes the "32 Bit VXI Register Based Interface
using Field Programmable Gate Arrays".  The Interface is implemented
as a C-size VXI (VME Extensions for Instrumentation) wirewrap card
that leaves a high percentage of the board space available for
whatever custom logic a user might wish to add.  The Interface
supports the following features as described in the VXI Bus
Specification, revision 1.3:  Register Based, Dynamic Configuration,
A16/A32 Addressing Mode, D08, D16, and D32 Data Paths, VME Block Mode
Transfers, Configuration Registers, VME Interrupts, and TTL Triggers.
The functions of the Interface can be logically divided into three
groupings:  Configuration and Addressing, Data bus and Registers and
Interrupts and Triggers.  These functions are implemented primarily
within two Field Programmable Gate Arrays (FPGAs).  The physical
characteristics of the Interface will also be described.

      Upon initial power up of a VXI system, a Resource Manager polls
all devices in order to determine the configuration of the system.
Block 1, "Dynamic Configuration" of Fig. 1 responds to this polling
by identifying itself as DC (Dynamic Configuration) capable and is
then assigned addresses, by the Resource Manager, in a manner similar
to the Programmable Option Select (POS) function of IBM's Micro
Channel Architecture.  Block 2, "Address Decode" uses this
information to decode the VXI bus during transfer cycles in order to
determine whether the transfer addresses the Interface or not.  The
net result is that only two si...