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DRAM Module Signal Margin Testing Based on Plate Voltage Modification

IP.com Disclosure Number: IPCOM000114062D
Original Publication Date: 1994-Nov-01
Included in the Prior Art Database: 2005-Mar-27
Document File: 2 page(s) / 56K

Publishing Venue

IBM

Related People

Galbi, DE: AUTHOR [+2]

Abstract

A signal margin testing technique for DRAM memory arrays is described. During the signal margin test mode, the signal in the array is lowered by modifying the voltage applied to the buried plate which is common to all cells in the array. Sub-standard cells are identified when they fail during marginal test. In the test mode, an externally applied voltage serves as the plate voltage so that characterization as a function of plate voltage can be obtained at either the wafer or module level.

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DRAM Module Signal Margin Testing Based on Plate Voltage Modification

      A signal margin testing technique for DRAM memory arrays is
described.  During the signal margin test mode, the signal in the
array is lowered by modifying the voltage applied to the buried plate
which is common to all cells in the array.  Sub-standard cells are
identified when they fail during marginal test.  In the test mode, an
externally applied voltage serves as the plate voltage so that
characterization as a function of plate voltage can be obtained at
either the wafer or module level.

      One of the requirements for signal margin testing is that VDD
not be changed since changing VDD will change the performance of
peripheral interface circuits.  This requirement takes on added
importance with designs intended for low supply voltages.  In the
signal margin testing scheme shown in the Figure, VDD remains at its
normal value, but the plate voltage connected in common to each of
the memory array capacitors is modified to reduce the signal voltage.

      In the standard operating mode, the GATING PAD shown in the
Figure may be used as a conventional signal input pad.  The standard
mode input signal passes through the GATING PIN RECEIVER and appears
as the STANDARD OUTPUT signal on the chip.  The plate voltage in the
standard operating mode is held at ground by the PLATE VOLTAGE
CONTROL block.

      In the signal margin test mode, the TEST MODE DECODE CIRCUITRY
detects a...