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Current Mode Level Shifter and Off Chip Receiver

IP.com Disclosure Number: IPCOM000114064D
Original Publication Date: 1994-Nov-01
Included in the Prior Art Database: 2005-Mar-27
Document File: 2 page(s) / 89K

Publishing Venue

IBM

Related People

Tretter, LL: AUTHOR

Abstract

Disclosed is a device that performs a level shift from one on chip voltage range to another voltage range for a received "off chip" signal. The method used to perform the level shift makes use of current mode techniques which will provide a much more robust circuit with respect to process variations and circuit component ranges.

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This is the abbreviated version, containing approximately 52% of the total text.

Current Mode Level Shifter and Off Chip Receiver

      Disclosed is a device that performs a level shift from one on
chip voltage range to another voltage range for a received "off chip"
signal.  The method used to perform the level shift makes use of
current mode techniques which will provide a much more robust circuit
with respect to process variations and circuit component ranges.

      This circuit uses "steered" current moving from one voltage
range, +5 volts and ground, to another voltage range, -5 volts and
ground, to accomplish the required level shift.  Because "current
mode" techniques are used the circuit described can be easily
modified for use with any symmetrical power supply values to very low
values.  This means the same topology can be easily "mapped" to new
lower voltage technologies.

      Referring to the circuit diagram for the invention, the input
A0 connects to PFET device T2.  Unlike the NFET devices the PFET
devices, in the Figure, have a fourth connection which represents the
N-WELL the device is constructed in.  This N-WELL, for the case of
T2, is connected to VH.  All of the PFET devices in the figure have
this fourth connection.  Depending on whether the device is operating
between VL and ground or ground and VH the well connection will be
connected to either ground or VH.  This fourth connection is not
shown on the NFET devices because these devices all share a common
substrate.  Diodes D1, D2, and D3 proved electro static discharge,
ESD, protection to the on chip FET device T2.  PFET T3 is the other
half of the differential pair T2/T3.  The gate of the T3 is connected
to a voltage divider formed by PFET devices T14 and T15.  This
divider provides a voltage reference half way between VH and ground.
The value of the voltage of the divider is a function of the external
technology the off chip receiver is interfacing with.  For external
CMOS circuits operating between GND and VH the value is VH/2.  If the
external logic circuits are TTL then the divider output value to the
gate of T3 would be 1.3 volts.  For this value of voltage a resistor
divider between VH and GND would be used.

      PFET devices T0 and T1 form a current mirror.  The reference
current for the mirror is generated by resistor R0 a...