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Method of Reducing the Nested-to-Isolated-Polysilicon Conductor Etch Bias

IP.com Disclosure Number: IPCOM000114073D
Original Publication Date: 1994-Nov-01
Included in the Prior Art Database: 2005-Mar-27
Document File: 2 page(s) / 27K

Publishing Venue

IBM

Related People

Adkisson, J: AUTHOR [+3]

Abstract

A process is described which reduces the Across-the-Chip Linewidth Variation (ACLV) in semiconductor Polysilicon Conductor (PC) lines that is caused by density differences between nested chip feature sites and isolated chip feature sites. The main cause of this nested-to-isolated etch bias is inconsistent sidewall passivation. The two-step process described below reduces ACLV by minimizing the amount of etching done with passivating chemistries.

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Method of Reducing the Nested-to-Isolated-Polysilicon Conductor Etch
Bias

      A process is described which reduces the Across-the-Chip
Linewidth Variation (ACLV) in semiconductor Polysilicon Conductor
(PC) lines that is caused by density differences between nested chip
feature sites and isolated chip feature sites.  The main cause of
this nested-to-isolated etch bias is inconsistent sidewall
passivation.  The two-step process described below reduces ACLV by
minimizing the amount of etching done with passivating chemistries.

      The first step in the process consists of a cap open/bulk etch
that uses a combination of a fluorine-containing gas (such as NF3 or
SF6) and a heavy, somewhat inert gas (such as N2 or Ar).  The first
step removes organic Anti-Reflective Coating (ARC), nitride, TEOS and
some of the polysilicon.  The second step is selective to the
underlying dielectric layer.  The use of the N2 or Ar in the first
step, combined with the selective etch of the second step, reduces
sensitivity to pattern-dependent loading.  The total process yields
an unanticipated reduction in ACLV.