Browse Prior Art Database

High Performance Master-Slave Interface

IP.com Disclosure Number: IPCOM000114077D
Original Publication Date: 1994-Nov-01
Included in the Prior Art Database: 2005-Mar-27
Document File: 2 page(s) / 76K

Publishing Venue

IBM

Related People

Yanes, JA: AUTHOR

Abstract

A method for reducing latency in a high performace master-slave interface is disclosed. Control and data paths in the bus master are paralleled.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 53% of the total text.

High Performance Master-Slave Interface

      A method for reducing latency in a high performace master-slave
interface is disclosed.  Control and data paths in the bus master are
paralleled.

This invention improves the performance for the master-slave
interface shown in Fig. 1.

The interface contains the following signals, as shown in Fig. 1.
  1.  Two byte-wide data transfer busses
  2.  Outbound signals, to provide control information from the
master
       to the slave
  3.  Inbound signals, to provide control information from the slave
to
       the master

The interface works in one of two operating modes:
  1.  For command and status transfer, one of the two byte-wide data
       transfer busses (bus 0) is configured for transfer from the
       master to the slave, while the other (bus 1) is configured for
       transfer from the slave to the master.  These busses, together
       with the controls lines, are controlled by microcode.  This
       allows full-duplex, relatively slow transfer of information
       between the master and the attached slave.
  2.  For data transfer, both data transfer busses are configured to
go
       in the same direction (from master to slave for WRITE, from
slave
       to master for READ).  These busses, together with the control
       lines, are controlled by data transfer hardware.  This allows
       half-duplex, high-speed transfer of information between the
       master and the attached slave.

      At the beginning of a data transfer operation, the hardware
must switch from full-duplex mode to half-duplex mode.  For a write
data transfer operation, the hardware utilized is shown in Fig. 2.
  1.  First the attached slave encodes the Inbound control signals to
       indicate that it has completed the previous command, and is
ready
       to receive the next command.
  2.  Next the master microcode loads the next command into the
  ...