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Browse Prior Art Database

Last Transfer Calculation for Different Bus Size Adapters

IP.com Disclosure Number: IPCOM000114090D
Original Publication Date: 1994-Nov-01
Included in the Prior Art Database: 2005-Mar-27
Document File: 4 page(s) / 113K

Publishing Venue

IBM

Related People

Johnson, MA: AUTHOR [+2]

Abstract

The task of calculating when the last bus transfer occurs in an adapter that is storing data to and from a FIFO RAM requires a complex algorithm to determine the occurance of the last RAM clock for different bus sizes. Restated, if the width of the RAM is greater than that of the data bus, the last RAM clock must have some "look-ahead" logic incorporated. This problem is solved with a unique but simple algorithm described herein.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 52% of the total text.

Last Transfer Calculation for Different Bus Size Adapters

      The task of calculating when the last bus transfer occurs in an
adapter that is storing data to and from a FIFO RAM requires a
complex algorithm to determine the occurance of the last RAM clock
for different bus sizes.  Restated, if the width of the RAM is
greater than that of the data bus, the last RAM clock must have some
"look-ahead" logic incorporated.  This problem is solved with a
unique but simple algorithm described herein.

      32 Bit bus
  o  L(0)&supplus.  = (DBLR>3 |  C(2)) & (A[0]&cplus.L(0))
  o  L(1)&supplus.  = (DBLR>3 |  C(2)) & (A(1)&cplus.L(1)&cplus.C(1))
  o  L(15-2)&supplus.  = L(15-2)  -  (DBLR>3 &  C(2))
  o  Last RAM Clock = (DBLR<=3 |  (DBLR=4 & A(1)  A(0))) &
     L(1)&supplus.  L(0)&supplus.

      There are two counting registers used in transferring data
to/from the adapter RAM and the destination/source memory.  They are:
  o  the Data_Buffer Length Register (DBLR, L(15-0)) and the
  o  the Data_Buffer Address Register (DBAR, A(31-0)).

In this case, the first register is assigned an initial 16 bit value
and counts down to zero to reach the end of the Data_Buffer in
memory, and the second register is assigned an initial 32 bit value
and counts up and is used to point to the Data_Buffer in memory.  The
following description shows the calculation of the Last RAM Clock in
terms of the values of bits in these registers.  The calculation of
the next value for the Data_Buffer Length Register is also given.  It
can be seen here that these two calculations share the same control
logic, thus the Last RAM Clock derivation costs nearly nothing in
chip real estate.  Tables 1, 2, and 3 give the next value of the
Data_Buffer Length Register (DBLR, L(15-0)) in terms of the DBLR and
the Data_Buffer Address Register (DBAR, A(31-0)).
  o  The C(n)  symbol is defined as the carry value of A(n-1)  +
      L(n-1).
     -  C(n)  = (A(n-1) & L(n-1)) | (A(n-1) & C(n-1)) | (L(n-1) & C(n-1)).
     -  C(0) = ZERO.
  o  The "&supplus."  character signifies t...